R&D Engineer

As an R&D Engineer in the TLR (top-level-route) team, you will be responsible for place and route, CTS, and routability analysis, focusing on congestion. Key duties include physical verification aspects like DRC, LVS, Antenna, LUP, chip finishing, and Tapeout. You will ensure RC requirements for manual/special signals, implement timing ECOs, IR drop fixes, RC extraction, and signal EM/Trans/Cap/Noise fixes. The role requires strong scripting skills in Perl and TCL, familiarity with Cadence Innovus and Calibre, and an understanding of VLSI fabrication processes. You will also be involved in integrity checks and post-Tapeout eJob view release, working closely with team members to achieve PD milestones.

Must Have

• Place and Route, CTS, Routability analysis with respect to congestion
• Well versed in physical verification aspect, DRC, LVS, Antenna, LUP, (chip finishing and Tapeout)
• Meeting RC requirements for manual/special signals
• Good understanding of Calibre DRC/LVS/DFM, DFY, ERC and ESD latchup
• Responsible for all the integrity checks (chip-finishing) and post Tapeout eJob view release
• Good scripting knowledge Perl and TCL, familiar with Calibre, Innovus
• Understanding of VLSI fabrication process
• Implementing timing ECOs, IR drop fixes, RC extraction, signal EM fixes, Trans, Cap, Noise fixes
• Open to new responsibilities in the context of rapid technological change
• Good communication skills, work closely with the team members to accomplish PD milestone

Good to Have

• Good understanding of CTS, STA, PTSI and timing
• Relevant experience of CAD tools Cadence Innovus, Calibre is preferred

Job description,

As part of TLR team (top-level-route), R&D Engineer is primarily responsible for :-

1) Place and Route, CTS, Routablity analysis with respect to congestion.

2) Well versed in physical verification aspect, DRC, LVS, Antenna, LUP, ( chip finishing and Tapeout)

3) Meeting RC requirements for manual/special signals

4) Good understanding of calibre DRC/LVS/DFM,DFY, ERC and ESD latchup.

5) Responsible for all the integrity checks (chip-finishing) and post Tapeout eJob view release,

6) Good scripting knowledge perl and TCL, familiar with calibre, Innovus,

7) Understanding of VLSI fabrication process,

8) Implementing timing ECOs. Implementing IR drop fixes, RC extraction, signal EM fixes, Trans, Cap, Noise fixes.

9) Open to new responsibilities in the context of rapid technological change.

10) Good communication skills, work closely with the team members to accomplish PD milestone.

11) Secondary competencies:- Good understanding of CTS, STA, PTSI and timing.

Relevant experience of CAD tools Cadence Innovus, Calibre is preferred.