Senior Engineer, Analog Layout

What You’ll Do

The Advanced Interconnect Lab (AIL) is seeking a self-driven and motivated professional qualified individual to join their team. The qualified individual will be responsible for research and development of a wide variety of cutting-edge circuits and architectures for optical interconnects, including analog front end, SERDES, ADC/DAC, etc

• Layout of Analog / High Speed transceiver circuit blocks such as amplifiers, drivers, ADC, DAC, LDO, PLL, filters, etc. in a timely manner.
• Layout of sensitive active / passive components including resistors, capacitors and inductors.
• Design verification including DRC, LVS, ERC and ANT and extraction.
• Block level floor planning with design engineers.
• Review and update layout for quality including signal integrity, power distribution and parasitic.

What You Bring

• BS and 5 years of relevant experience MS in 3years of relevant experience preferred
• 5+ years analog layout experience in deep sub-micron and FinFET processes.
• Experience in floor planning and layout of analog blocks such as amplifiers, drivers, ADC, DAC, LDO, PLL, filters, etc.
• Solid knowledge in device structures.
• Understand tradeoffs in matching, coupling, parasitic effects, area, etc.
• Understand causes and preventions of ESD and latch-up.
• Proficient in interpreting verification DRC, LVS, ERC, ANT results.
• Working knowledge of Cadence Virtuoso and Mentor Calibre required.
• Team player with excellent communication skills.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.

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