Senior Principal Design Engineer

Your Team, Your Impact

Marvell Compute and Custom Solutions has been at the forefront of developing and delivering leading edge, high-performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast-growing product lines, Marvell technology is powering the next-generation data processing and workload acceleration platforms for the Carrier, Cloud/Enterprise and Datacenter market segments.

The proliferation of the data economy is accelerating and creating significant strains on the global data infrastructure. Built on decades of expertise and execution, Marvell’s custom ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide-array of flexible business models.

What You Can Expect

• Design, develop, implement, verify, and document micro-architecture and RTL for complex designs in the networking domain with strong focus on Ethernet.
• Work closely with system and chip architects to design high-quality, zero-defect and A0 implementations.
• Participate in the full design development cycle, end-to-end, from writing micro-architecture docs, RTL coding, specifications of timing, closely work with design verification teams to review test plans and execution of test, ability to bring up block tests on silicon during lab testing, and maintenance of designed blocks and reusable IPs.
• Produce comprehensive block uArchitecture and register Specs.
• Schedule detailed reviews with cross-functional teams Evaluate and participate in improving design and verification methodologies.
• Supervise or mentor other digital design engineers.

What We're Looking For

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience. Master’s degree in Computer Science, Electrical Engineering or related fields with 10-12 years of experience. PhD in Computer Science, Electrical Engineering or related fields with 8-10 years of experience.
• Creating micro-architectural specs from standards, architectural specifications.
• System Verilog RTL coding with System Verilog Assertions.
• Creating modular/reusable design components.
• Ability to multi-task and must be flexible and adaptable to a rapidly changing and demanding environment.
• Demonstrated success in project leadership.
• Experience in the following areas is MUST: Ethernet - low speed and High speed, MacSec, Networking Domain
• Low power design.
• High speed designs
• Strong passion to drive and work on cutting-edge enhancements in Ethernet and hyper scalers.