Senior Silicon Design Engineer

21 Minutes ago • 8 Years +

Software Development & Engineering

Job Description

The Senior Silicon Design Engineer will perform physical design implementation of custom IP and SoC designs from RTL to GDS, preparing designs for manufacturing. This involves synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power/noise analysis. The role includes verification and signoff, analyzing results to fix violations, and optimizing designs for power, frequency, and area. The engineer will also contribute to physical design methodologies and flow automation.

Good To Have:

Knowledge of Industry standard protocols - PCIE, USB, DRR.
Experience with Low power/UPF implementation/verification techniques.
Experience with Formal verification techniques.

Must Have:

Perform physical design implementation of custom IP and SoC designs from RTL to GDS.
Conduct all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
Conduct verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
Analyze results and make recommendations to fix violations.
Possess expertise in structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.
Optimize design to improve product-level parameters such as power, frequency, and area.
8+ years of experience with complex ASIC/SOC Implementation.
Solid understanding of system and processor architecture, and the interaction of computer hardware with software.
Experience designing and implementing complex blocks like CPUs, GPU, Media blocks, and Memory controller.
Experience with System Verilog/SOC development environment.
Strong background in scripting - PERL, TCL, Python.
Understanding of Hardware validation techniques.

Perks:

Fully home-based work model

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Job Description:

Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to fix violations for current and future product architecture. Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools. Optimizes design to improve productlevel parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.

Qualifications:

Btech/Mtech with 8+ years of experience with complex ASIC/SOC Implementation.
Solid understanding of system and processor architecture, and the interaction of computer hardware with software.
Experience designing and implementing complex blocks like CPUs, GPU , and Media blocks and Memory controller.
Experience with System Verilog/SOC development environment.
Strong background in scripting - PERL,TCL, Phyton.
Understanding of Hardware validation techniques
Knowledge of Industry standard protocols - PCIE, USB, DRR, etc, preferable.
Experience with Low power/UPF implementation/verification techniques preferable
Experience with Formal verification techniques is preferable.