Senior SOC Design Engineer - Physical Design and Integration

1 Month ago • 4 Years +
System Design

Job Description

Join Intel's Client Engineering Group to design Client SOCs for next-generation laptop and desktop computers. This role involves researching, designing, developing, and testing lead Intel designs, focusing on SoC physical design. Responsibilities include SoC, clock, and power delivery integration, performance optimization, physical synthesis, place and route, clock tree synthesis with Synopsys or Cadence tools, static timing analysis, and multiple power domain analysis. The ideal candidate is a self-motivated problem-solver with excellent communication skills, capable of collaborating in a high-paced team.
Good To Have:
  • 6+ years of experience in backend design and/or integration product development and delivery on leading edge process nodes
Must Have:
  • SoC, clock design, and power delivery integration
  • Drive performance optimization, including co-optimization work with process teams, to create best-in-class designs.
  • Physical synthesis, place and route, and clock tree synthesis with Synopsys or Cadence tools.
  • Static timing analysis constraint understanding and generation, clock stamping, and timing closure.
  • Multiple Power Domain analysis using standard Power Formats UPF or CPF.
  • Bachelor’s Degree in Electrical Engineering, Computer Engineering or a related field with 6+ years of relevant experience -OR- Master’s Degree in Electrical Engineering, Computer Engineering or a related field with 4+ years of relevant experience.
Perks:
  • Competitive pay
  • Stock
  • Bonuses
  • Health benefits
  • Retirement benefits
  • Vacation

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communication
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Job Description:

Do Something Wonderful!

Intel put Silicon in Silicon Valley. No one else is obsessed with engineering and has a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.

Who We Are

Come join Intel's Client Engineering Group responsible for designing Client SOCs that make up more than half of Intel's annual revenue. We envision the future of computing and design for the next generation of laptop and desktop computers. We are looking for SoC (System on Chip) Physical Design Engineer ready to research, design, develop, and test lead Intel designs as we reimagine how to build SOCs at Intel and in the semiconductor industry.

Who You Are

This role is within Intel's highly regarded Devices Development Group, headquartered in Portland, Oregon with additional sites in Penang, Malaysia, and Bangalore, India. Our bold purpose as a company is to create world-changing technology that enriches the lives of every person on earth, and this role is instrumental in furthering our mission to shape the future of technology.

Your responsibilities may include but not be limited to:

  • SoC, clock design, and power delivery integration
  • Drive performance optimization, including co-optimization work with process teams, to create best-in-class designs.
  • Physical synthesis, place and route, and clock tree synthesis with Synopsys or Cadence tools.
  • Static timing analysis constraint understanding and generation, clock stamping, and timing closure.
  • Multiple Power Domain analysis using standard Power Formats UPF or CPF.

The ideal candidate will exhibit behavioral traits that indicate:

  • Self-motivator with strong problem-solving skills
  • Excellent interpersonal skills, including written and verbal communication
  • Ability to work as part of a team and collaborate in a high-paced

Qualifications:

You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

  • Bachelor’s Degree in Electrical Engineering, Computer Engineering or a related field with 6+ years of relevant experience -OR- Master’s Degree in Electrical Engineering, Computer Engineering or a related field with 4+ years of relevant

Preferred Qualifications

  • 6+ years of experience in backend design and/or integration product development and delivery on leading edge process nodes

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, Oregon, Hillsboro

Additional Locations:

Business group:

The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003

Annual Salary Range for jobs which could be performed in the US:

$177,200.00-$250,160.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

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