Senior Staff ASIC Physical Design Engineer

2 Days ago • 4-10 Years

Job Summary

Job Description

This role involves complete ownership of the Physical Design and Network Routing (PNR) implementation, including floor planning, placement, and clock tree synthesis, as well as sign-off activities such as Static Timing Analysis (STA), power analysis, and formal verification. The engineer will lead a team of Physical Block designers, collaborating with them and post-silicon teams to resolve issues and ensure timely project execution. The engineer should have at least 4 years of experience. They should also possess strong analytical and communication skills, including technical leadership and coaching skills.

Must have:

10+ years of Physical Design/Hardware Engineering experience.
Very good knowledge of Floor Planning, PNR and STA flows.
Very good knowledge of Placement/Clock Tree Synthesis (CTS).
Good understanding of low power designs (LEC/CLP).
Strong analytical skills and ability to work in a team.
Excellent written and verbal communication skills.

4 skills required

4 skills required for this role

Add these skills to join the top 1% applicants for this job

unix

linux

communication

team-player

Job Details

Company:

Qualcomm France S.A.R.L.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

About the Role

Qualcomm modem team is looking for a world-class Physical Design engineer looking to work on cutting edge wireless technology, which will be deployed worldwide in our industry’s leading devices.

Responsibilities include:

Complete ownership on PNR implementation (Floor Planning, Placement, Clock Tree Synthesis, Post Route, …) and signoff (STA, Power Analysis, Formal Verification, Low power Verification, IR Drop, DRC, LVS, …)
Leading a team of Physical Block designers
Working collaboratively with block designers, implementation, and post-silicon teams to resolve issues and ensure timely project execution.

What are we looking for?

Bachelor/Master’s degree in science, engineering, or related field
10+ years of Physical Design / Hardware Engineering experience or related work experience
Very good knowledge of Floor Planning, PNR and STA flows
Very good knowledge of Placement/Clock Tree Synthesis (CTS)
Good understanding of low power designs (LEC/CLP)
Very good knowledge of sign-off tools (DRC, LVS, IRDrop)
Experience with ASIC top level (Top level floor planning, pad ring, interface with packaging team)
Good knowledge on Unix/Linux – TCL fundamentals/scripting
Strong analytical skills and ability to work in a dynamic and fast paced team environment
Excellent written and verbal skills
Strong interpersonal skills and a good team player
Strong technical leadership and coaching skills

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

*References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.

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