Senior Staff Engineer - Physical Design

45 Minutes ago • 12 Years +

Job Summary

Job Description

The Senior Staff Engineer - Physical Design will perform hands-on physical design and verification tasks in advanced process nodes, manage ASIC development flow setup, and coordinate full chip physical design activities. Responsibilities include floor-planning, place and route, CTS, timing closure, IR/EM analysis, and LEC for block level and full chip designs, as well as creating scripts for DRC, LVS, DFM, Antenna and density checks. The role also involves mentoring junior team members and reporting to the ASIC Design Director.
Must have:
  • 12+ years of experience in ASIC/SoC Physical Design.
  • Experience with advanced FinFET node designs.
  • Experience with Cadence PnR/STA tools and Calibre.
Perks:
  • Competitive Compensation Package
  • Restricted Stock Units (RSUs)
  • Provisions for advanced education
  • Medical Insurance and Wellness Benefits
  • Educational Assistance
  • Advance Loan Assistance
  • Office lunch & Snacks Facility

Job Details

The Opportunity We're looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. What You'll Do:
  • Perform hands-on physical design and physical verification tasks across projects in advanced process nodes.
  • Manage project-specific ASIC development flow setup and maintenance.
  • Physical design tasks include floor-planning, place and route, CTS, timing closure, IR/EM analysis, and LEC for block level and full chip flat/hierarchical designs. Coordinate full chip physical design and verification activities.
  • Physical verification tasks include creating setup and scripts for DRC, LVS, DFM, Antenna and density checks, report generation, analysis, debugging, and implementing fixes in the physical design database.
  • Ensure correct IP and pad-ring integration in block and flat designs.
  • Mentor junior PD/PV team members and oversee their tasks.
  • You will be reporting to ASIC Design Director.
What You'll Need:
  • Minimum 12+ Years of experience in ASIC/ SoC Physical Design.
  • Skills – have working experience in advanced FinFET node designs.
  • Experience with Cadence PnR/STA tools and Calibre; good scripting/automation skills is a must.
  • Education – B. Tech /M. Tech in Electronics Engineering.
'"We have a flexible work environment to support and help employees thrive in personal and professional capacities" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes:
  • Competitive Compensation Package
  • Restricted Stock Units (RSUs)
  • Provisions to pursue advanced education from Premium Institute, eLearning content providers
  • Medical Insurance and a cohort of Wellness Benefits
  • Educational Assistance
  • Advance Loan Assistance
  • Office lunch & Snacks Facility
Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

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About The Company

We work to create silicon that enables the highest performing, most reliability and lowest power digital communication networks.

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