Silicon Architecture/Design Engineer
5 Months ago • Upto 2 Years
Software Development & Engineering
Job Description
As a Silicon Architect/Design Engineer at Google, you'll contribute to the advancement of TPU technology for AI/ML applications. Responsibilities include characterizing ML workloads, developing architecture specifications, creating power/performance models, designing microarchitectures and RTL, and collaborating with hardware/software teams for codesign. You will also develop advanced AI/ML capabilities, implement efficient verification strategies, and optimize physical design processes. The role involves optimizing for performance, power, features, schedule, and cost, and contributing to silicon bring-up and qualification. This is a crucial role in shaping the future of AI/ML hardware acceleration at Google.
Good To Have:
- 2+ years post-PhD experience
- Experience with performance modeling tools
- Knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies
- Knowledge of high-performance and low-power design techniques
Must Have:
- PhD in relevant engineering field
- Experience with accelerator architectures and data center workloads
- Proficiency in C++, Python, Verilog, Synopsys, Cadence tools
- Develop architecture specifications
- Develop power/performance models
Minimum qualifications:
- PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering or related technical field, or equivalent practical experience.
- Experience with accelerator architectures and data center workloads.
- Experience in programming languages (e.g., C++, Python, Verilog), Synopsys, Cadence tools.
Preferred qualifications:
- 2 years of experience post PhD.
- Experience with performance modeling tools.
- Knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies.
- Knowledge of high performance and low power design techniques.
About the job
In this role, you will shape the future of AI/ML hardware acceleration as a Silicon Architect/Design Engineer and drive cutting-edge TPU (Tensor Processing Unit) technology that fuels Google's most demanding AI/ML applications. You will collaborate with hardware and software architects and designers to architect, model, analyze, define and design next-generation TPUs. You will have dynamic, multi-faceted responsibilities in areas such as product definition, design, and implementation, collaborating with the Engineering teams to drive the optimal balance between performance, power, features, schedule, and cost.The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
- Revolutionize Machine Learning (ML) workload characterization and benchmarking, and propose capabilities and optimizations for next-generation TPUs.
- Develop architecture specifications that meet current and future computing requirements for AI/ML roadmap. Develop architectural and microarchitectural power/performance models, microarchitecture and RTL designs and evaluate quantitative and qualitative performance and power analysis.
- Partner with hardware design, software, compiler, Machine Learning (ML) model and research teams for effective hardware/software codesign, creating high performance hardware/software interfaces.
- Develop and adopt advanced AI/ML capabilities, drive accelerated and efficient design verification strategies and implementations.
- Use AI techniques for faster and optimal Physical Design Convergence -Timing, floor planning, power grid and clock tree design etc. Investigate, validate, and optimize DFT, post-silicon test, and debug strategies, contributing to the advancement of silicon bring-up and qualification processes.
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