Silicon Low Power Design Engineer, TPU, Google Cloud

10 Months ago • 5 Years +

Research Development

Job Description

This role involves developing cutting-edge SoCs for machine learning computation in Google data centers. Responsibilities include defining power management schemes, creating power specifications, performing power estimations, running optimization tools, and collaborating with cross-functional teams. The ideal candidate will have 5+ years of ASIC/SoC development experience with a focus on power optimization, including low-power schemes, power roll-up, and estimations. Experience with ASIC design verification, synthesis, and timing analysis is essential. The work contributes to the innovation behind Google's products, shaping the next generation of hardware experiences focused on performance, efficiency, and integration.

Good To Have:

Python, C/C++, Perl programming
SoC designs and integration flows
Power optimization and modeling tools
High-performance, low-power design techniques

Must Have:

5+ years ASIC/SoC development experience
Power optimization expertise
Low-power schemes, power roll-up, estimations
ASIC design verification, synthesis, timing analysis

Add these skills to join the top 1% applicants for this job

cpp

python

perl

innovation

cross-functional

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
5 years of experience in ASIC/SoC development, with a focus on Power optimization.
Experience handling Low Power schemes, power roll up, and power estimations.
Experience with ASIC design verification, synthesis, and timing analysis.

Preferred qualifications:

Experience with programming languages (e.g., Python, C/C++ or Perl).
Experience in SoC designs and integration flows.
Experience with power optimization and Power modeling tools.
Knowledge of high performance and low power design techniques.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will be part of a team developing cutting-edge SoCs used to accelerate machine learning computation in data centers. You'll solve technical problems with innovative and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind. You will collaborate with members of architecture, verification, power and performance, physical design etc. to specify and deliver high quality designs for next generation data center accelerators.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

Participate in defining power management schemes and low power modes.
Create power specifications and UPF definition for SoC and subsystems.
Perform power estimation, roll, up and tracking through all phases of the project.
Run power optimization tools, suggest ways to improve power, and drive convergence.
Work with cross-functional teams for smooth handoff of power intent and power projections.