SoC Fabric Architect

Join Rivos Inc., a well-funded exciting start-up whose mission is to create industry transforming RISC-V based and accelerated computing platforms with HW/SW co-design. We offer a creative, flexible, and fun-filled environment where your work and innovation is prized and contributes to our mission. This role involves working closely with various teams to define and optimize fabric architectures, including inter- and intra-chip interconnects and coherent/non-coherent protocols, while considering power, performance, area, and timing goals.

Must Have

• Knowledge of SoC architectures, caching hierarchy, and memory subsystems
• Understanding of on-chip and off-chip topologies and interconnects
• Experience with cache-coherent and non-coherent protocols
• Proficiency with functional and performance simulators for design space exploration
• Relevant design experience demonstrating architectural/performance/power trade-offs

Join Rivos Inc., a well-funded exciting start-up whose mission is to create industry transforming RISC-V based and accelerated computing platforms with HW/SW co-design. We offer a creative, flexible, and fun-filled environment where your work and innovation is prized and contributes to our mission.

Responsibilities

• You will be working closely with architects, micro-architects, and software, performance, validation, and physical design teams to own or actively participate in:
• Architectural definition and specification of fabrics:

• Inter- and intra-chip interconnects
• Coherent, non-coherent, and bridging protocols
• Working with SoC architects to optimize fabrics for overall system architecture
• Developing, assessing, and refining fabric architectures with appropriate trade-off analysis to target power, performance, area, and timing goals
• Helping produce and review validation plans for functionality and performance

Requirements

• Knowledge of SoC architectures including caching hierarchy and memory subsystems, with relevant experience
• Understanding of on-chip and off-chip topologies and interconnects with experience in architecture and design relevant subsystems
• Knowledge of and experience with cache-coherent and non-coherent protocols (e.g., directory based implementations to resolve conflicts, deadlocks, etc.)
• Experience with functional and performance simulators: design space exploration, modeling and analysis, knowledge of tools
• Relevant design experience exemplifying architectural/performance/power trade-offs.

Education and Experience

• Ph.D.: 3-5 years experience, or
• Master’s: 5-7 years industry experience, or
• Bachelor’s: 7-10 years industry experience