Be part of PCIe/CXL verification IP team and development efforts of the most complex industry leading software solutions for hardware/SOC memory and protocol verification. Responsible for software development and validation of PCIe/CXL Verification IP. Participate in development efforts of the PCIe/CXL product to meet customer use model, solution requirements, protocol specification and execute necessary SW development practices to create reusable robust software solution to enable verification of these interface protocols. Work with multi-site and diverse team. You need to effectively collaborate multi location development team to contribute in PCIe/CXL verification IP development, milestones technical roadmap and people training for success. Work with technical support lead and key customers to resolve implementation or usage issues as Cadence VIP products are used within various verification environments and timing critical to our customer’s successes.