Sr Principal Design Engineer -- Memory Modeling Portfolio

4 Months ago • All levels

Software Development & Engineering

Job Description

This position requires a candidate with a MSEE or equivalent and extensive industry experience in designing complex protocols and/or hardware systems. Excellent communication skills, both written and spoken English are essential. The candidate must possess fluent and extensive RTL design knowledge using Verilog/SystemVerilog, along with experience using RTL verification tools and flows. Solid debugging skills are also required, along with emotional intelligence and collaboration abilities. The role involves scheduling workload, planning tasks, and coordinating with others. Experience with Cadence simulation and/or emulation products and scripting languages is strongly recommended. Familiarity with memory sub-system design and operation is also highly desired. The candidate will be involved in work that matters, helping solve what others can’t.

Good To Have:

Verification experience using Cadence simulation and/or emulation products.
Programming experience with scripting languages like Perl, TCL, C-shell.
Experience in memory sub-system design and operation.

Must Have:

MSEE or equivalent with industry experience.
Excellent written and spoken English communication skills.
Fluent RTL design knowledge using Verilog/SystemVerilog.
Experience with RTL verification tools and flows.
Strong debugging skills.
Emotionally intelligent collaborator and communicator.

Add these skills to join the top 1% applicants for this job

communication

problem-solving

excel

game-texts

agile-development

shell

perl

system-design

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Essential: The position requires MSEE, or equivalent, with significant and deep industry experience in designing complex protocols and/or hardware systems. MUST have excellent communication skills with both written and spoken English. Fluent and extensive RTL design knowledge using Verilog/SystemVerilog is required along with experience using RTL verification tools and flows. Must excel in and demonstrate solid debugging experience/skills. Emotionally intelligent collaborator and communicator. Experience with team-wide collaboration tools and processes. Drive and ability to schedule workload and plan own tasks effectively as well as coordinate with and adapt to other's needs and priorities when needful. Agile! Adaptive!

Strongly recommended: Verification experience using Cadence simulation and/or emulation products is highly desired. Programming experience with scripting languages like Perl, TCL, C-shell is strongly recommended. Experience in memory sub-system design and operation is strongly recommended.