Staff ASIC Modem Design Engineer

1 Day ago • 2-8 Years

Job Summary

Job Description

The Staff ASIC Modem Design Engineer role at Qualcomm involves designing and integrating blocks within the modem. Responsibilities include microarchitecture development, RTL design and ownership, and collaboration with various teams to resolve issues. The engineer will be involved in the early high-level architectural exploration, micro architectural research and arriving at a detailed specification. The role also requires debugging, providing workarounds, and making recommendations on bug fixes. The candidate will be expected to work on cutting edge wireless technology that will be deployed worldwide. The candidate needs to work in a dynamic and fast paced team environment.

Must have:

RTL design (Verilog), System Verilog skills
Experience with modem related blocks
Simulation and Code coverage tools
Strong analytical and interpersonal skills

Good to have:

Experience with ASIC ECO flow
Experience with C++/SystemC

6 skills required

6 skills required for this role

Add these skills to join the top 1% applicants for this job

shell

python

communication

team-player

cross-functional

problem-solving

Job Details

Company:

Qualcomm France S.A.R.L.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Role and Responsibilities

Qualcomm modem team is looking for world-class RTL design engineers looking to work on cutting edge wireless technology, which will be deployed worldwide in our industry leading devices.

You will be contributing to RTL design and integration of blocks inside our modem.

Responsibilities include:

Microarchitecture development and specification. From early high-level architectural exploration, through micro architectural research and arriving at a detailed specification.
RTL ownership. Development, assessment, and refinement of RTL design to target power, performance, area, and timing goals
Working collaboratively with block designers, verification, architecture, implementation, and post-silicon teams to resolve issues and ensure timely project execution.
Collaborating with cross-functional teams, debugging and identifying issues, providing workarounds, and making recommendations on bug fixes.

Skillset required

Bachelor/Master’s degree in science, engineering, or related field
RTL design (Verilog), System Verilog, Python/Tcl shell-scripting skills
Simulation and Code coverage tools (Xcelium, Verdi, Modeltech/Questa, …)
8+ years of RTL design experience on-chip with custom digital logic
Experience with modem related blocks (4G, 5G, …)
Gate level Simulation debug
Lints and Clock Domain Crossing checks
Exposure to synthesis and STA
Experience with ASIC ECO flow is a plus
Experience with C++/SystemC is a plus
Strong analytical skills and ability to work in a dynamic and fast paced team environment
Excellent written and verbal skills
Strong interpersonal skills and a good team player
Strong technical leadership and coaching skills

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

*References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.

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