Job Description
- Knowledge of System Verilog Interfaces.
- Knowledge of Lint checks.
- Strong knowledge in Scan Insertion, Compression, ATPG, Memory BIST, JTAG for mixed signal designs.
- Experience with Mentor DfT tools and Synopsys simulator tools.
- Ability to define DFT Strategy and Requirement Specification.
- Experience in DfT verification for gate-level and timing simulations.
- Hands-on experience solving DfT problems, simulation failures, ATPG coverage, and DRC improvements.
- Experience defining timing constraints for DfT modes, including Primetime.
- Proficiency in RTL coding, shell/Perl scripting.
- Experience handling analog IP DfT simulations.
- Fluency with common DfT concepts and tools.
Strong knowledge and experience in Scan Insertion, Compression, ATPG, Memory BIST and JTAG at IC level for mixed signal designs
Experience in using Mentor DfT tools, and Synopsys simulator tools.
Define DFT Strategy and Requirement Specification for the design
DfT verification for gate-level and timing simulations
Work cross-site with the design team to define and implement DfT.
Hands-on experience in solving DfT problems, simulation failures, ATPG coverage, and DRC improvements.
Work with the STA engineer to define timing constraints for DfT modes. Hands-on experience on Primetime will be required.
Work with the Layout engineer to ensure DFT logic is implemented without issues.
Support the Test engineer in silicon debug and pattern delivery for ATE.
Experience in RTL coding, shell/Perl scripting.
Knowledge of System Verilog Interfaces and Lint checks preferred.
Experienced in handling analog IP DfT simulations.
Be fluent with all common concepts of DfT and DfT tools.
