STAFF IP DFT Verification Engineer

54 Minutes ago • 6 Years +

Testing

Job Description

Broadcom's ASIC Product Division is seeking a highly skilled HBM and SerDes DFT Verification Engineer to join their dynamic team. This role involves implementing and verifying DFT methodologies for HBM, DDR, and SerDes designs, collaborating with design and architecture teams to define testability requirements. The engineer will utilize advanced simulation tools, analyze DFT-related data for continuous improvements, and document verification processes. Key responsibilities also include generating, verifying, and debugging test vectors, assisting with silicon failure analysis, and innovating new DFT solutions for 3nm IPs and beyond.

Good To Have:

Experience working on ATE.
Familiarity with BIST logic for array and link testing.
Knowledge of AHB/APB/AXI buses.

Must Have:

Implement and verify DFT methodologies for HBM, DDR, and SerDes designs.
Collaborate with design and architecture teams to identify and define critical testability requirements.
Utilize advanced simulation tools and methodologies to thoroughly verify DFT implementations.
Analyze DFT-related data and provide insights for continuous design improvements.
Document verification processes, results, and best practices.
Stay updated with the latest trends and technologies in DFT, HBM, and SerDes.
Work closely with STA and DI Engineers for design closure for test.
Generate, verify, and debug test vectors before tape release.
Validate and debug test vectors on ATE during the silicon bring-up phase.
Assist with silicon failure analysis, diagnostics, and yield improvement efforts.
Interface with customers, physical design, and test engineering/manufacturing teams globally.
Work closely with I/P DFT engineers and other stakeholders.
Debug customer returned parts on the ATE.
Innovate newer DFT solutions to solve testability problems in 3nm IPs and beyond.
Automate DFT and Test Vector Generation flows.
Strong DFT background (Analog DFT, MBIST, IEEE1687).
Proven experience in DFT verification, particularly with HBM, DDR, PCIE and other SerDes IPs.
Understanding of DFT methodologies, including scan, BIST, and ATPG.
Proficiency in simulation tools and scripting languages (e.g., Perl, Python, TCL and Ruby).
Excellent analytical and problem-solving skills.
Strong communication and teamwork abilities.
Ability to work in a multi-disciplined, cross-department environment.
Solid knowledge in analog and digital circuit design, and device physics fundamentals.
Excellent problem solving, debug, root cause analysis and communication skills.

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Job Description:

Broadcom's ASIC Product Division is seeking candidates for HBM/DDR/SERDES Verification Lead Engineer position at our San Jose, California Development Center. We are seeking a highly skilled HBM and SerDes DFT Verification Engineer to join our dynamic team. In this role, you will play a crucial part in ensuring the robustness and reliability of our HBM, DDR and SerDes designs through comprehensive Design for Test (DFT) verification strategies. You will work collaboratively with cross-functional teams to develop, implement, and validate DFT methodologies, guaranteeing that our products meet the highest quality standards.

Key Responsibilities:

Implement and verify DFT methodologies specifically for HBM, DDR and SerDes designs.
Collaborate with design and architecture teams to identify and define critical testability requirements.
Utilize advanced simulation tools and methodologies to thoroughly verify DFT implementations.
Analyze DFT-related data and provide insights for continuous design improvements.
Document verification processes, results, and best practices to enhance team knowledge and efficiency.
Stay updated with the latest trends and technologies in DFT, HBM, and SerDes to drive innovation within the team.
Working closely with STA and DI Engineers design closure for test
Generating, Verifying & Debugging Test vectors before tape release.
Validating & Debugging Test vectors on ATE during the silicon bring up phase
Assisting with silicon failure analysis, diagnostics & yield improvement efforts
Interfacing with the customers, physical design and test engineering/manufacturing teams located globally
Working closely with I/P DFT engineers & other stakeholders
Debugging customer returned parts on the ATE
Innovating newer DFT solutions to solve testability problems in 3nm IPs & beyond
Automating DFT & Test Vector Generation flows

Skills/Experience:

Strong DFT background (such as Analog DFT, MBIST, IEEE1687 and others)
Proven experience in DFT verification, particularly with HBM, DDR, PCIE and other SerDes IPs.
Understanding of DFT methodologies, including scan, BIST, and ATPG.
Proficiency in simulation tools and scripting languages (e.g., Perl, Python, TCL and ruby).
Excellent analytical and problem-solving skills.
Strong communication and teamwork abilities.
The ability to work in a multi-disciplined, cross-department environment
Solid knowledge in analog and digital circuit design, and device physics fundamentals
Excellent problem solving, debug , root cause analysis and communication skills
Experience working on ATE is a plus
Familiarity with BIST logic for array and link testing is a plus
Knowledge of AHB/APB/AXI buses is a plus

Education & Experience:

Bachelors in Electrical/Electronic/Computer Engineering and 8+ years of relevant industry experience or Masters Degree in Electrical/Electronic/Computer Engineering and 6+ years of relevant industry experience

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