Job Description
This position requires a Digital ASIC/Processor Design Engineer with 1-3 years of experience. The responsibilities include leading and mentoring junior engineers, working with various teams worldwide from Post-RTL to Netlist release, and focusing on area, timing, power, and testability. The engineer will write timing constraints, perform synthesis, formal verification, CLP, and Primetime. They will also optimize datapath design for low-area, low-power, and high-speed using advanced synthesis features and handle complex digital blocks in advanced process nodes.
Must Have:
- 1-3 years experience in Digital ASIC / Processor Design.
- Strong fundamentals in Microarchitecture, Computer Arithmetic, Circuit Design, Process Technology.
- Strong communication skills to work with design teams worldwide.
- Extensive experience in Synthesis, Formal Verification, Conformal Low Power, PTPX, Primetime, Conformal ECO.
- Extensive experience in UPF based power intent and synthesis.
1-3 years experience in Digital ASIC / Processor Design
- Strong fundamentals in core areas: Microarchitecture, Computer Arithmetic, Circuit Design, Process Technology
- Strong communication skills to work with design teams worldwide- Extensive experience in Synthesis (DC or Genus), Formal Verification (LEC / Formality), Conformal Low Power, PTPX, Primetime, Conformal ECO
- Extensive experience in UPF based power intent and synthesis
- - High-speed and Low-power 5G and WLAN Modem Hardmacro Implementation Lead
- Lead, train and mentor team of junior engineers to execute on a complex project for a large modem design in advanced process nodes
- Work closely with RTL, DFT and PD leads worldwide to take a project from Post-RTL to Netlist release, and converge on area, timing, power and testability
- Primary tasks include writing timing constraints, synthesis, formal verification, CLP, Primetime, PTPX, CECO
- Optimize datapath design for low-area, low-power and high-speed using advanced features in synthesis such as MCMM, SAIF, multibit mapping etc.
- Optimize PPA using the right tool options and stdcell libraries / memories
- Handle complex digital blocks with >1M gates in advanced process nodes from 4nm / 5nm / 7nm / 8nm
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