Tenstorrent

CPU Core Regression Debug Engineer

Deep Learning Library Developer'

CPU Core Feature Verification and Debug Engineer

Tenstorrent seeks a CPU Core Regression Debug Engineer with 7+ years of experience in high-performance OOO CPU microarchitecture. Must have expertise in debugging RTL and DV, proficiency in waveform and log file analysis, and strong knowledge of assembly, C/C++, and UVM. Experience with ISAs, simulation, emulation, and scripting is essential.

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 About the job
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 The Tenstorrent team combines technologists from different disciplines who come together with a shared passion for AI and a deep desire to build great products. We value collaboration, curiosity, and a commitment to solving hard problems.Find out more about our culture. CPU verification engineer driving core level regression debug, triage and responsible for the functional sign-off for the core. <ul><li>Functional verification with emphasis on core level regression debug and triage for simulation and emulation regressions</li><li>Hands-on debug for core level failures. Propose and implement stimulus enhancements and debug capability improvements for core, cluster and chip level testbench environments</li><li>Primary owner for driving bug hunting using all available stimulus generators. Analysis of bugs found and proposing not only stimulus but also configuration and coverage changes</li><li>Drive core level regression environment enhancements to improve the overall productivity for the team</li><li>Develop detailed core level verification plans by understanding both ISA and microarchitectural specifications for the design</li><li>Support design deployment across simulation and emulation platforms</li><li>Develop random and directed stimulus that spans pre-silicon, emulation and post-silicon domain</li><li>Work with design, test and post silicon validation teams to ensure high quality delivery of the entire CPU core / cluster</li></ul>
 <ul><li>BS/MS/PhD in EE/ECE/CE/CS with at least 7+ years of experience</li><li>Strong background and experience with high performance OOO CPU microarchitecture</li><li>Experience and understanding of one or more ISAs - x86, ARM or RISCV</li><li>Significant experience debugging RTL and DV in a simulation environment, proficient at waveform and log file based debug</li><li>Experienced with assembly, C/C++ and UVM based stimulus generation targeting both ISA and microarchitectural scenarios</li><li>Familiar with simulation, formal and emulation environments</li><li>Hands-on with scripting (Python, PERL)</li><li>Experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator)</li><li>Strong problem solving and debug skills across various levels of design hierarchies</li></ul>
 Locations: Bangalore, India Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
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