Analog Circuit Team Lead

30 Minutes ago • 8 Years +

Job Summary

Job Description

Lead the design and development of high-speed SERDES and advanced power management circuits. Define architecture and specifications for analog/mixed-signal IPs. Oversee schematic design, simulation, layout supervision, and post-layout verification. Collaborate with cross-functional teams to ensure first-pass silicon success. Drive design reviews, documentation, and sign-off processes. Mentor junior engineers and align design goals with product requirements.
Must have:
  • Lead design and development of high-speed SERDES and advanced power management circuits.
  • Define architecture and specifications for analog/mixed-signal IPs.
  • Oversee schematic design, simulation, layout supervision, and post-layout verification.
  • Collaborate with digital, layout, and verification teams.
  • Drive design reviews, documentation, and design sign-off processes.
  • Mentor and guide junior engineers.
  • Interface with other teams and internal stakeholders.
  • BSc./M.Sc. in Electrical Engineering.
  • 8+ years of experience in analog/mixed-signal IC design, with at least 2 years in a leadership role.
  • Proven track record in designing and delivering SERDES and power management IPs in advanced CMOS nodes (e.g., 7nm, 5nm).
  • Strong understanding of signal integrity, power integrity, and layout-aware design.
  • Proficiency in EDA tools (Cadence Virtuoso, Spectre, EMIR tools, etc.).
  • Excellent communication, leadership, and project management skills.

Job Details

Job Description:

Lead the design and development of high-speed SERDES and advanced power management circuits (e.g., DC-DC, LDOs converters, switched-capacitor regulators, etc...). Define architecture and specifications for analog/mixed-signal IPs. Oversee schematic design, simulation, layout supervision, and post-layout verification. Collaborate with digital, layout, and verification teams to ensure first-pass silicon success. Drive design reviews, documentation, and design sign-off processes. Mentor and guide junior engineers, fostering a culture of technical excellence and innovation. Interface with other teams and internal stakeholders (System, Post Silicon validation, production and reliability) to align design goals with product requirements.

Qualifications:

BSc./M.Sc. in Electrical Engineering 8+ years of experience in analog/mixed-signal IC design, with at least 2 years in a leadership role. Proven track record in designing and delivering SERDES and power management IPs in advanced CMOS nodes (e.g., 7nm, 5nm). Strong understanding of signal integrity, power integrity, and layout-aware design. Proficiency in EDA tools (Cadence Virtuoso, Spectre, EMIR tools, etc.). Excellent communication, leadership, and project management skills.

Job Type:

Experienced Hire

Shift:

Shift 1 (Israel)

Primary Location:

Israel, Petah-Tikva

Additional Locations:

Business group:

The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

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