Job Description:

Person will be responsible for driving DFT implementation in Wireless SoC chips. The person will have full ownership of ATPG architecture, design, implementation, verification and deployment to Silicon testing, working with Test engineer. The responsibilities also include MBIST design, implementation and verification for all memories in the SoC. Person should be capable of generate and debug DFT patterns on tester. Work closely with the design, design-verification, and backend teams to enable the integration an validation of the test logic in all phases of the design, and backend implementation flow.

Experience Level:

8-10 years

Education Requirements:

B.Tech/M.Tech in ECE, EEE

Minimum Qualifications:

• Full-chip DFT working experience with multiple design Tape Outs
• Expert knowledge of DFT architecture on complex Design with multiple clock domains.
• Experience in ATPG for pattern generation and simulation of Test Transition faults, Stuck-at, IDDQ, at-speed faults .
• Hands-on experience in industry standard DFT tools - Mentor Tessent suite or Synopsys DFT compiler.
• Block level and Chip level SCAN insertion, DRC, Coverage Analysis and improvements.
• Expertise in Scan Compression(EDT/OPMISR+), MBIST, ATPG implementation and verification.
• Expert knowledge on Test time reduction.
• Good Knowledge of cross functional domains (SYN, LEC, STA, PD) with owner ship of constraints developments & LEC.
• Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process
• Experience working with cross functional global teams
• Experience in Low-Power DFT requirements.
• Experience in Low-Power MBIST architectures and Memory testing.

Preferred Qualifications:

• Experience in DFT related RTL integration.
• Excellent communication and analytical skills
• Experience in leading junior teams, Mentoring/Training and Project leadership.
• Exceptional problem-solving skills