High Performance DSP Core Implementation Engineer, Sr Lead

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General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

• Looking for a highly talented and a technically strong leader with an eye for quality to lead a high performing and talented team of engineers in the implementation domain for Display Sub-System.
  • Able to handle multiple project execution that are time critical and complex
  • Able to communicate effectively with all stakeholders across the organization
  • Able to collaborate with cross functional teams for upholding the best practices and enabling smooth execution
  • Focus on improving execution efficiency and improve on the optimizations in area, power and performance.
  • Able to grow the team in terms of technical depth and size as we do more and more projects
  • Able to innovate and bring fresh ideas
• Bachelor’s or master’s degree in engineering with 9-13+ Years of experience.
• Should have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools.
• Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure.
• Experience in all aspects of timing closure for multi-clock domain designs.
• Should be familiar with MCMM synthesis and optimization.
• Should have good understanding of low-power design implementation using UPF.
• Experience with scripting language such as Perl/ Python, TCL.
• Experience with different power optimization flows or technique such as clock gating.
• Should be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation
• Should be able to handle ECOs and formal verification and maintain high quality matrix

Responsibilities include:

• Synthesis, LEC, Low power checks, Memory BIST insertion, Constraints validation.
• Development of signoff quality constraints and the development of power intent constraints.
• May also include running RTL Lint, CLP, MEMBIST, DFT DRC etc.

• TCL script development in addition to running/analyzing/debugging designs.
• Hands on with Synopsys DCG/Genus/Fusion Compiler.
• Hands on with Synopsys Prime Time including constraint development for complex blocks with multiple clock domains.
• Hands on with Cadence Conformal LEC and Cadence Conformal Low Power including UPF development
• Experience with either RTL development or Physical Design is also a plus

Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

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If you would like more information about this role, please contact Qualcomm Careers.