Power UPF Methodology Engineer

38 Minutes ago • 10 Years + • Software Development & Engineering • $181,100 PA - $318,400 PA

Job Summary

Job Description

As part of our Digital Design Engineering group, you'll transform imaginative and revolutionary ideas into reality by applying engineering fundamentals. You'll design state-of-the-art ASICs, focusing on transistor-level power ERC sign-off and UPF implementation & verification for mobile SOCs. This role involves integrating new insights, supporting transistor-level power ERC sign-off for digital and mixed-signal designs, and enhancing power sign-off methodologies for future mobile products. Key responsibilities include driving mixed-signal IP power ERC and verification, ensuring power intent coverage, defining and developing power ERC frameworks, and liaising with CAD and verification teams.
Must have:
  • Bachelor's degree in a relevant field
  • Minimum of 10 years of relevant industry experience
  • Experience in ASIC design methodology with a focus on power definition
  • Familiarity with Caliber based ERC flows
  • Knowledge of scripting languages (Tcl, Perl, Python)
Good to have:
  • Experience in ASIC design flows and custom IP design flows
  • Familiarity with power intent definition, implementation, and verification flows
  • Familiarity with power analysis and optimization methods
  • Familiarity with entire RTL2GDS flow
  • Strong communication skills
Perks:
  • Stock options
  • Discounted Apple stock purchase
  • Comprehensive medical and dental coverage
  • Retirement benefits
  • Discounted products and free services
  • Reimbursement for certain educational expenses

Job Details

Power UPF Methodology Engineer

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