Design Engineering Architect

The Design Engineering Architect at Cadence will lead a team of verification engineers for interconnect IP, contributing technically as needed. Key responsibilities include crafting and reviewing verification plans, managing execution for complex designs, and ensuring verification closure. The role involves close collaboration with cross-functional teams and talent acquisition to expand the team.

Must Have

• Manage a team of verification engineers for interconnect IP
• Crafting and reviewing verification plan
• Manage overall execution on verification plans to verify highly complex and configurable designs
• Responsible for verification closure and sign off
• Work closely with cross functional teams (DV/Arch/Design/PD/GUI)
• 15+ years of design verification experience
• BS (or higher) in EE/Computer Engineering
• Experience in managing a team of 5+ engineers
• Experience in hiring and building the team, training and developing engineers
• Excellent knowledge of Interconnects, NoCs and design verification fundamentals
• Thorough understanding of System Verilog, UVM, and other programming languages to build flexible and reusable complex testbenches
• Strong technical skills to review the code, make constructive suggestions and overall ability to maintain the codebase
• Experience with development of fully automated flows, manage regression cycles and monitor coverage progression

Good to Have

• Relevant experience in interconnect and subsystems
• Exposure to scripting languages like Perl, Unix shell or similar languages

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Responsibilities

• Manage a team of verification engineers for interconnect IP. Also required to pitch in with the technical contributions as required.
• Relevant experience in interconnect and subsystems is strongly preferred
• Crafting and reviewing verification plan. Manage the overall execution on those plans to verify highly complex and configurable designs.
• Responsible for verification closure and sign off.
• Work closely with cross functional teams (DV/Arch/Design/PD/GUI).
• Identify and hire talent to grow the team as needed.

Required Skills and Experience:

• 15+ years of design verification experience
• BS (or higher) in EE/Computer Engineering
• Experience in managing a team of 5+ engineers.
• Experience in hiring and building the team, training and developing engineers.
• Strong interpersonal skills. Excellent at identifying and communicating requirements, delegating tasks.
• Excellent knowledge of Interconnects, NoCs and design verification fundamentals.
• Thorough understanding of System Verilog, UVM, and other programming languages to build flexible and reusable complex testbenches.
• Strong technical skills to review the code, make constructive suggestions and overall ability to maintain the codebase to avoid future technical debt.
• Experience with development of fully automated flows, manage regression cycles and monitor coverage progression.
• Exposure to scripting languages like Perl, Unix shell or similar languages would be a plus.

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About Us

Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.