Design Verification Engineer
4 Months ago • All levels • $166,600 PA - $296,300 PA
Software Development & Engineering
Job Description
As a Design Verification Engineer, you will ensure bug-free silicon for a part of the SoC/IP. You will develop detailed test and coverage plans based on micro-architecture and verification methodologies suitable for the IP, ensuring a scalable and portable environment. This includes developing the verification environment, including stimulus, checkers, assertions, trackers, and coverage. You will create verification plans for all features, execute them, and debug test failures. You will also develop block, IP, and SoC level test benches, tracking and reporting progress using metrics like bugs and coverage.
In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will get to develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Furthermore, you will develop verification plans for all features under your care, execute verification plans, including design bring-up, DV environment bring- up, regression enabling features, and debug of the test failures. You will also learn to develop block, IP and SoC level test-benches track and report DV progress using a variety of metrics, including bugs and coverage.
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