Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
As a Digital IC Design Staff Engineer, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You’ll be part of a digital team of about eight people making a big impact on this organization, working on ultra-dense and performance Static Random Access Memory (SRAM) memory compilers.
This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates.
Your role involves conducting in-depth circuit analysis for compact sub-circuit blocks within our overall design, considering Process, Voltage, and Temperature (PVT) factors. Using your experience using transistor-level circuit design software like Cadence Virtuoso or Spectre X for design analysis, you will be mentoring others to optimize performance within specified area and power constraints, utilizing engineering judgment to balance trade-offs and refine designs. Your day-to-day activities include iterative testing, documentation, summarization of findings, and collaboration with the global team through regular meetings, ensuring alignment within the 18-month project cycles. Tools such as Python, Perl, and the Microsoft Office Suite will be integral to your tasks, and proficiency in a Linux environment is essential for seamless execution.
To be successful in this role, you must:
• Responsible engineer for at least one major sub-circuit block from architecture definition to fine tuning.
• Identifies and proposes innovative solutions to enhance the design of at least one major sub-circuit block.
• Participates in root cause investigation and silicon validation of model to hardware correlation issues.
• Mentors and coaches new and/or less experienced team members.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Interview Integrity
As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.
Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
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