Digital IC Design, Staff Engineer (SYN/STA)
2 Months ago • 6 Years +
Job Description
This Staff Engineer position focuses on Digital IC Design, specifically in Synthesis (SYN) and Static Timing Analysis (STA). The role involves performing logic synthesis for multi-million gate ASIC projects, executing ECOs and formal verification, and collaborating with logic design and PnR teams. Responsibilities also include managing schedules, maintaining synthesis scripts, and contributing to IC design flow development. Candidates should have experience with commercial implementation tools and scripting languages.
Good To Have:
- Experience in timing constraint development and timing constraint debug.
- Experience in Conformal ECO flow.
- Experience with PnR tools.
Must Have:
- Perform logic synthesis at sub-system or top level for multi-million gate ASIC projects.
- Perform ECO and formal verification.
- Work with logic design and PnR engineers on logic, timing, power and physical issues.
- Manage schedules and support cross-functional engineering effort.
- Implement, enhance and maintain synthesis scripts.
- Contribute to the continuous development of IC design flow.
- 6+ years of experience in logic synthesis for ASIC/SoC projects.
- Familiarity with IC design flow.
- Experience with commercial tools for logic synthesis (DC, Genus), formal verification (LEC, Formality), STA (PrimeTime, Tempus).
- Experience with synthesizable Verilog and/or VHDL codes.
- Experience in Linux environment and scripting languages like Perl, TCL.
- Knowledge of area, speed, power optimizations during logic synthesis.
- Good written and oral communication skills in English.
Perks:
- Competitive compensation
- Great benefits
- Workstyle within an environment of shared collaboration, transparency, and inclusivity
- Tools and resources to succeed
- Opportunities to grow and develop
Your Team, Your Impact
Storage BU - Vietnam
What You Can Expect
- Perform logic synthesis at sub-system or top level for multi-million gate ASIC projects
- Perform ECO (Engineering-Change-Order) and formal verification
- Work with logic design and PnR engineers on logic, timing, power and physical issues.
- Manage schedules and support cross-functional engineering effort.
- Implement, enhance and maintain synthesis scripts.
- Contribute to the continuous development of IC design flow
What We're Looking For
- BS/MS in Electrical Engineering/Computer Engineering, or related fields and 6+ years of experiences working on logic synthesis for multi-million-gate ASIC/SoC projects. Newly graduated candidate with 7+ GPA is also welcome.
- Very familiar with IC design flow.
- Experiences in commercial implementation tools for logic synthesis (DC, Genus), formal verification (LEC, Formality), STA (PrimeTime, Tempus).
- Experience of synthesizable Verilog and/or VHDL codes.
- Experience in Linus environment and writing/using scripting languages such as Perl, TCL, etc.
- Knowledge of area, speed, power optimizations during logic synthesis.
- Self-motivated and excited to learn new skills, tools, IP, and design flows.
- Good written and oral communication skills in English.
- Experience in timing constraint development and timing constraint debug is a plus
- Experience in Conformal ECO flow, PnR tools is plus
Additional Compensation and Benefit Elements
With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
#LI-UN1
Set alerts for new jobs by Marvell
Set alerts for new jobs in Vietnam
