DSP R&D Engineer

5 Hours ago • 3 Years + • $108,000 PA - $172,800 PA
Audio Engineering

Job Description

Develop specifications, architecture, and micro-architecture for digital signal processing and communications algorithms. Responsibilities include bit-exact C/C++ and MATLAB/Simulink system modeling, simulation, and verification with RTL. Define and document chip requirements, architecture, verification, and lab test plans. Perform lab testing and debug of ASICs. Requires expertise in Digital Communication Theory and Digital Signal Processing algorithms, with experience in C/C++ and MATLAB/Simulink.
Good To Have:
  • Experience in equalizers & timing recovery
  • Experience architecting communications systems for high performance ASIC based products
Must Have:
  • Develop specification, architecture, and micro-architecture of digital signal processing and communications algorithms
  • Bit-exact C/C++ and MATLAB/Simulink system modeling and simulation
  • Develop and run system level simulation suites of the transceivers and perform vector matching verification with RTL
  • Define and document chip requirements, architecture, verification and lab test plan
  • Lab testing and debug of ASICs
  • PhD and 3+ years of related experience or Master in Digital Signal Processing in Electrical Engineering and 6+ years of related experience
  • Expertise in Digital Communication Theory & Digital Signal Processing algorithms
  • Experience in C/C++, MATLAB/Simulink
Perks:
  • Discretionary annual bonus
  • Equity
  • Medical, dental and vision plans
  • 401(K) participation including company matching
  • Employee Stock Purchase Program (ESPP)
  • Employee Assistance Program (EAP)
  • Company paid holidays
  • Paid sick leave
  • Vacation time
  • Paid Family Leave and other leaves of absence

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Job Description:

Responsibilities include:

  • Develop specification, architecture, and micro-architecture of digital signal processing and communications algorithms
  • Bit-exact C/C++ and MATLAB/Simulink system modeling and simulation
  • Develop and run system level simulation suites of the transceivers and perform vector matching verification with RTL
  • Define and document chip requirements, architecture, verification and lab test plan
  • Lab testing and debug of ASICs

Requirements:

  • PhD and 3+ years of related experience or Master in Digital Signal Processing in Electrical Engineering and 6+ years of related experience
  • Expertise in Digital Communication Theory & Digital Signal Processing algorithms
  • Experience in C/C++, MATLAB/Simulink
  • Experience in equalizers & timing recovery is highly desirable
  • Experience architecting communications systems for high performance ASIC based products is desirable
  • Good hands-on skills in the lab
  • Good oral and written communication skills

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is $108,000 - $172,800

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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