Engineer Internship: Generation of analog models from a library of basic building blocks (M/F)

52 Minutes ago • All levels

Research Development

Job Description

NXP Semiconductors is seeking an electronics engineering intern for a 6-month end-of-study project in Toulouse. The role involves enhancing mixed-signal verification methodologies for automotive integrated circuits within the DES division. Key responsibilities include studying existing analog blocks, analyzing a library of basic analog function models, creating simple and complex analog models from this library, and exploring automation for model creation using generative AI tools. The ideal candidate is in their final year of an electronics engineering program with strong knowledge in digital and analog circuit design, and modeling languages like VerilogA, Verilog AMS, or System Verilog, along with good English proficiency.

Good To Have:

Knowledge of EDA tools like Cadence Virtuoso, Cadence Xcelium
Interest in AI technologies and automation

Must Have:

Study of existing analog blocks
Analysis of a library of basic analog function models
Creation of simple and then complex analog models based on this library
Exploration of automation for model creation using generative AI tools
Digital and analog electronic design
Modeling language like verilogA, verilog AMS or System Verilog
Good ability to synthesize concepts and have a system view
Good verbal and written communication skills in English and French
Good English level

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Context

NXP Semiconductors offers connections and infrastructure for a smarter world and offers solutions for an easier, better and safer life. As a global leader in secure connectivity solutions for embedded applications, NXP is the driver of innovation for the secure connected vehicle.

The verification team of the DES division (Drivers & Energy Systems) based in Toulouse is in charge of verifying integrated Analog and Mix Signals (AMS) circuits for the automobile, and to ensure its conformity with the customer’s specification before its manufacture. We wish to improve our innovative methodologies of mixed verification, in order to participate in this objective of continuous improvement we are looking for a trainee of end of study over a period of 6 months.

Your responsibilities

The trainee will be responsible for/perform one or more of the following tasks :

Study of existing analog blocks
Analysis of a library of basic analog function models
Creation of simple and then complex analog models based on this library
Exploration of automation for model creation using generative AI tools

Your profile

Education level : Master Degree / last year of engineering school in electronics
Knowledge required in:
Digital and analog electronic design
Modeling language like verilogA, verilog AMS or System Verilog
Good ability to synthesize concepts and have a system view
Good verbal and written communication skills in English and French
Knowledge of one or more EDA tools is a plus: Cadence Virtuoso, Cadence Xcelium
Interest in AI technologies and automation
A good level of English is required.