Senior/Lead DFT Engineer

NXP is seeking a Senior/Lead DFT Engineer with 10+ years of experience in SoC DFT implementation and verification. The role involves working with scan architectures, JTAG, boundary scan, memory BIST, ATPG, and LBIST. Candidates should be proficient in Verilog/VHDL RTL coding, automation, and Mentor DFT tool sets, with experience in Synopsys tools. Responsibilities include scan insertion, ATPG DRC, coverage analysis, simulation debug, and post-silicon debug, having worked on multiple SoCs from start to finish.

Must Have

• 10+ years experience in SoC DFT implementation and verification of scan architectures, JTAG, boundary scan, memory BIST, ATPG and LBIST.
• BE/ME/B.Tech/M.Tech from reputed institutes with relevant industry experience.
• Well versed in Verilog/VHDL RTL coding and automation.
• Experienced in using Mentor DFT tool sets and reasonable acquaintance with Synopsys’s scan insertion and timing analysis tools along with standard linting tools.
• Hands-on experience in scan insertion, JTAG, LBIST, ATPG DRC and coverage analysis, Simulation debug with timing/SDF and post silicon debug.
• Must have worked on more than one SoC, from start to end.

Good to Have

• Proactive, collaborative, self driven and detail-oriented capable of exercising independent judgment.
• Experience on debug and root cause the problem in simulation failures and silicon.
• Self-motivation, flexibility, with strong interpersonal skills.
• Effective communication skills, oral and written skills.
• Show an engaged curiosity, a will to understand the mechanisms behind the effects, an eagerness to constantly learn and improve.

Perks & Benefits

• Online and offline learning opportunities to help you develop some of your core and professional skills.
• Commitment to sustainability and making measurable year-on-year progress.
• Inclusive work environment with programs focused on diversity, inclusion and equality.

• Senior DFT engineer preferably with 10+ yrs experience in SoC DFT implementation and verification of scan architectures, JTAG, boundary scan, memory BIST, ATPG and LBIST.
• BE/ME/B.Tech/M.Tech from reputed institutes with relevant industry experience
• The engineer should be well versed in Verilog/VHDL RTL coding, automation, experienced in using Mentor DFT tool sets and reasonable acquaintance with Synopsys’s scan insertion and timing analysis tools along with standard linting tools.
• The engineer needs to have hands-on experience in scan insertion, JTAG, LBIST, ATPG DRC and coverage analysis, Simulation debug with timing/SDF and post silicon debug.
• Must have worked on more than one SoC , from start to end.
• Must be proactive, collaborative, self driven and detail-oriented capable of exercising independent judgment
• The engineer with experience on debug and root cause the problem in simulation failures and silicon
• Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills
• Show an engaged curiosity, a will to understand the mechanisms behind the effects, an eagerness to constantly learn and improve

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Career Development Opportunities

Bright Minds. Bright Futures.

We believe that a key component to growing our business is to develop our people. To enable you to grow your career at NXP, we offer online and offline learning opportunities to help you develop some of your core and professional skills.

Commitment At NXP.

We recognize NXP is a powerful change agent as we continue to deliver innovative solutions that advance a more sustainable future. We remain steadfast in our commitment to sustainability and making measurable year-on-year progress. Also, we aim to create an inclusive work environment and we will not tolerate racism, discrimination or harassment of any kind. We have programs in place focused on diversity, inclusion and equality.