Performs timing analysis and timing optimization, generates, and verifies timing constraints, and fixes timing violations at chip/block level for SoCs. Conducts timing rollups, designs for functionality, and develops performance and power optimized clock networks. Develops and defines methodologies to ensure highest quality of timing models that enable the physical design team to operate efficiently. Defines the right process, voltage, and temperature (PVT) conditions to be used for timing analysis for a given design based on the product plans such as operating conditions and binning. Works closely with the clocking team and other backend full chip designers for clocking balance, timing fixes, power delivery, and partitioning. Collaborates with architecture, clocking design, and logic design teams to deliver flow development for chip integration and validates high performance low power clock network guidelines.
The Full Chip Timing (FCT) Design Automation team plays a critical role in supporting all aspects of full chip timing integration. Our mission is to enable seamless timing closure and optimization across the entire backend flow. We develop and maintain automation environments, tools, and methodologies that ensure high-quality timing models and constraint management.
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This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
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