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Layout Design Engineer, Silicon

Layout Design Engineer, Silicon

1 Month ago • 5-10 Years • Research & Development • Undisclosed

About the job

2 skills required for this role

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data-structures

innovation

Job Description

This role involves designing and drawing layouts of high-speed/low-power memories in 3nm (or equivalent) technology nodes. Responsibilities include analyzing design specifications, developing custom memory arrays or standard-cells, drawing schematics, running simulations, improving PPA of memory arrays, and collaborating with the Physical Design team. The ideal candidate will have 5+ years of experience in layout verification (DRC, LVS, etc.) and experience with memory array layout components (row decoders, write drivers, etc.). The work contributes to the development of custom silicon solutions for Google's direct-to-consumer products.

Must have:

Bachelor's degree in VLSI or equivalent
5+ years experience in high-speed/low power memory layout design
5+ years experience in layout verification (DRC, LVS, etc.)
Experience with 3nm (or equivalent) technology nodes
Develop custom memory arrays or standard-cells
Run simulations and improve PPA

Good to have:

Master's degree in VLSI or related field
Experience with Virtuoso XL and Star-RC/QFS
Understanding of layout design rules and DFM
Experience with sense amplifiers, decoders, and other memory components

Minimum qualifications:

Bachelor’s degree in VLSI, Computer Engineering, or equivalent practical experience.
5 years of experience designing and drawing layout of high-speed/low power memories.
5 years of experience with layout verification activities like DRC, LVS, Latch-Up, or EMIR and Density Checks.
Experience with developing memory array layout (e.g., row decoders, write drivers, assist circuits, sense amplifiers, memory control circuit) in 3nm (or equivalent) technology nodes.

Preferred qualifications:

Master's degree in VLSI, Computer Engineering, or a related field.
Experience drawing layout for sense amplifiers, decoders, assist circuits, latches, flip-flops, isolation cells, power switches, and level shifters.
Experience with placement, track planning and integration of various blocks within SRAM memories.
Experience with Virtuoso XL and Extraction tools such as Star-RC/QFS.
Understanding of layout design rules, layout dependent effects and DFM in FinFET technology nodes.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

Analyze design specifications from Compute IP's and develop custom memory arrays or standard-cells.
Draw schematics, extract layout, write spice deck and run spice simulations to validate the circuit (or block).
Run high-speed sigma analysis to understand sensitivity of designed circuit.
Work with layout engineers to improve the Performance, Power, Area (PPA) of memory arrays or standard-cells.
Collaborate with Physical Design team and ensure seamless integration of standard-cells or memory arrays.

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About The Company

Google

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A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.