Lead Design Engineer

2 Months ago • All levels • Software Development & Engineering

Job Summary

Job Description

The Lead Design Engineer will be responsible for hands-on layout experience in various analog IPs such as Opamps, Bandgaps, Data converters, LDO, and PLL. They will need to understand layout effects on circuits including speed, capacitance, power, and area. Knowledge of analog layout techniques, DSM technology, and experience with 28nm and below technology nodes are required. The candidate must have good communication skills, be a team player, and scripting/automation experience is a plus. They will also need to have experience with high-speed analog, data converters, power management, and PLL. They should also possess strong analytical and problem-solving skills.
Must have:
  • Hands-on layout experience in analog IPs.
  • Understanding of layout effects on circuit performance.
  • Knowledge of analog layout techniques.
  • Good understanding of DSM technology.
  • Experience with 28nm and below technology nodes.
  • Good communication skills and ability to be a team player.
Good to have:
  • Scripting and automation experience.
  • Experience with high-speed analog, data converters, power management, and PLL.

Job Details

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Responsibilities Hands on layout experience in various analog IP like Opamps, Bandgaps, Data converters, LDO and PLL etc. Understanding layout effects on the circuit such as speed, capacitance, power and area etc., Knowledge of various analog layout techniques like matching, shielding etc., Good understanding of DSM technology methodology, issues etc., Having worked on latest technology nodes, 28nm and below, is desired. Must have good communication skills and should be team player. Scripting and automation experience is a plus. Hands on layout experience in various analog IP like High speed Analog (Serdes), Data converters, power management and PLL etc. Understanding layout effects on the circuit such as speed, capacitance, power, and area etc., Knowledge of various analog layout techniques, floorplan constraints and IP integration at chip level scenario. Good understanding of DSM technology methodology, issues etc., Having worked on latest technology nodes, 28nm and below, is desired. Must have good communication skills and should be team player. Scripting and automation experience are a plus. Good communication skills, documentation, and presentation skills. Strong analytical and problem-solving skills. Qualifications BE/BTech/ME/MS/MTech in Electrical/ElectronicsBehavioral skills required Must possess strong written, verbal and presentation skills Ability to establish a close working relationship with both customer peers and management Explore what’s possible to get the job done, including creative use of unconventional solutions Work effectively across functions and geographies Push to raise the bar while always operating with integrity

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About The Company

Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

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