The Lead Design Engineer will be responsible for hands-on layout experience in various analog IPs such as Opamps, Bandgaps, Data converters, LDO, and PLL. They will need to understand layout effects on circuits including speed, capacitance, power, and area. Knowledge of analog layout techniques, DSM technology, and experience with 28nm and below technology nodes are required. The candidate must have good communication skills, be a team player, and scripting/automation experience is a plus. They will also need to have experience with high-speed analog, data converters, power management, and PLL. They should also possess strong analytical and problem-solving skills.
Good To Have:- Scripting and automation experience.
- Experience with high-speed analog, data converters, power management, and PLL.
Must Have:- Hands-on layout experience in analog IPs.
- Understanding of layout effects on circuit performance.
- Knowledge of analog layout techniques.
- Good understanding of DSM technology.
- Experience with 28nm and below technology nodes.
- Good communication skills and ability to be a team player.