Sr Principal Design Engineer

Cadence is seeking a Sr Principal Design Engineer to design, develop, and support IP models for system-level memory (SDRAM, NAND Flash, eMMC, SD Card, DFI, UFS) for hardware-based verification products. The role involves RTL design, verification, and documentation of memory IP, requiring an MSEE with at least 5 years of experience in complex protocol/hardware system design. Strong Verilog/SystemVerilog, RTL verification, and debugging skills are essential, along with excellent communication and collaboration abilities.

Must Have

• Responsible for scheduling, designing, developing, and supporting IP models of system level memory (SDRAM, NAND Flash, eMMC, SD Card, DFI, UFS).
• Update, maintain, document, and support existing system level memory model products.
• Perform RTL design, verification, productizing, and documentation of memory IP.
• Interface with internal and external customers on emulation, simulation, or verification problems.
• Collaborate on cross verification and training in memory IP, ensuring product quality.
• MSEE or equivalent with minimum 5 years experience in designing complex protocols/hardware systems.
• Excellent written and spoken English communication skills.
• Fluent and extensive RTL design knowledge using Verilog/SystemVerilog.
• Experience using RTL verification tools and flows.
• Solid debugging experience and skills.
• Emotionally intelligent collaborator and communicator.
• Ability to schedule workload, plan tasks effectively, and adapt to priorities.

Good to Have

• Verification experience using Cadence simulation and/or emulation products.
• Programming experience with scripting languages like Perl, TCL, C-shell.
• Experience in memory sub-system design and operation.

Key Responsibilities

• Responsible for scheduling, designing, developing, and supporting IP models of system level memory such as SDRAM (LPDDR, HBM), NAND Flash (ONFI/QSPI/OSPI), eMMC, SD Card, DFI, and UFS models for use on hardware based verification products.
• Also responsible for updating, maintaining, documenting, and supporting existing system level memory model products.
• Perform as individual contributor for RTL design, verification, productizing, and documentation of memory IP.
• Interface with internal and external customers to work on diverse problems and solutions related to emulation, simulation, or verification.
• Perform as team member toward cross verification of and cross training in memory IP as well as in developing and using lifecycle processes to ensure product quality.

Job Requirements:

• The position requires MSEE, or equivalent, with a minimum of 5 years significant experience in designing complex protocols and/or hardware systems.
• MUST have excellent communication skills with both written and spoken English.
• Fluent and extensive RTL design knowledge using Verilog/SystemVerilog is required along with experience using RTL verification tools and flows.
• Must excel in and demonstrate solid debugging experience/skills.
• Emotionally intelligent collaborator and communicator. Experience with team-wide collaboration tools and processes.
• Drive and ability to schedule workload and plan own tasks effectively as well as coordinate with and adapt to other's needs and priorities when needful. Agile! Adaptive!
• Verification experience using Cadence simulation and/or emulation products is a PLUS.
• Programming experience with scripting languages like Perl, TCL, C-shell is a PLUS.
• Experience in memory sub-system design and operation is a PLUS.