Lead Product Engineer (EMIR / PDN Analysis & Power Integrity)

4 Months ago • Upto 5 Years

Product Management

Job Description

As a Lead Product Engineer at Cadence, you will be part of the product engineering team focused on Power Noise Reliability analysis within the Multiphysics Systems BU. Your responsibilities will include building expertise in power integrity, 3DIC analysis & optimization, AI-driven IR mitigation, and electrothermal optimization for digital designs. You will collaborate with R&D to facilitate the development of these methodologies and flows, while also supporting strategic customers. This role requires a strong background in digital logic design, CMOS logic design, power IR drop analysis, circuit design and analysis, and digital/behavioral simulation fundamentals. Debugging low-power and multiple power domain analysis is crucial. Experience with 3DIC design and methodologies is a plus.

Good To Have:

Experience with 3DIC design and methodologies.
Ability to debug Timing and thermal issues in relation to IR and EM

Must Have:

5+ years industry experience in EMIR and PDN analysis.
Strong background in digital logic and CMOS design.
Knowledge of power IR drop analysis and circuit design.
Excellent debugging skills for critical issue identification.
Ability to solve interface level IC and System analysis problems.
Knowledge on TCL, Perl or Python scripting.

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Responsibilities
•   Be part of the product engineering team working on Power Noise Reliability analysis platform within Multiphysics Systems BU at Cadence.
•   Build domain expertise in power integrity , 3DIC analysis & optimization , Industry’s first AI driven IR mitigation & fixing methodology , electrothermal optimization for digital designs.
•   Work closely with R&D to facilitate the development of these methodologies and flows.
•   Responsibilities also including supporting strategic customers and functional product engineering driving solutions in the Multiphysics space.

Qualifications
•   Bachelor’s Degree in Electrical / Electronics / Electronics and Communication / VLSI Engineering with 5 years related experience
•   OR Masters with 2 - 3 years of related experience
•   OR PhD with 0+ years of related experience

Experience and Technical Skills required
•   5+ years relevant industry experience in EMIR analysis, PDN analysis with digital signoff tools and Digital Physical implementation as designer or methodology/flow expert.
•   Strong background in Digital logic Design, CMOS logic Design, Power IR drop analysis, Circuit Design and Analysis, Digital and Behavioral simulation fundamentals related to IC and Package Design.
•   Debugging of Low power and multiple power domain analysis for chip power integrity sign-off.
•   Experience with 3DIC design and methodologies is a plus.
•   Must have excellent debugging skills and ability to separate out the critical issues from trivial ones.
•   Ability to solve interface level problems emanating from IC Implementation side and System analysis side.
•   Ability to debug Timing and thermal issues in relation to IR and EM is a plus.
•   Knowledge on TCL, Perl or Python scripting.

Behavioral skills required
•   Must possess strong written, verbal and presentation skills.
•   Ability to establish a close working relationship with both customer peers and management.
•   Explore what’s possible to get the job done, including creative use of unconventional solutions.
•   Work effectively across functions and geographies.
•   Push to raise the bar while always operating with integrity.