Low Power ASIC Engineer (Next-Gen, High-Speed Memory Subsystem)

Qualcomm is the world leader in wireless ICs powering the majority of 4G and 5G devices and the largest fabless semiconductor company in the world.

Qualcomm is looking for bright ASIC engineers with excellent analytical and technical skills, and a focus on low power, high performance ASIC designs, and, ability to execute critical power analysis of critical design IPs for path to DDR. This is a great opportunity to join a fast-paced SoC team responsible for development of next Generation, high performance, low power Memory Subsystem RTL Design, flows and methodology for high performance ASICs in sub-4nm process for mobile, automotive, compute, AI and XR space.

An ideal candidate will oversee definition, design, verification, and documentation for ASIC development for a variety of products. Determines architecture design, logic design, and system simulation. Provides technical expertise for next generation initiatives.

Responsibilities

• Work with cross-functional teams to deliver high performance and low power designs.
• Identify key power use cases and work with verification team to create and simulate power tests.
• Analyze and estimate power for the key use cases using PowerArtist and PrimeTime PX (PTPX) and work with cross-functional teams - design, implementation, and physical design teams - to optimize power.
• Project power numbers and establish budgets at the project outset and work with design teams throughout the project cycle to optimize and keep power on target. Track and deliver power data to other cross-functional teams.
• Build power models based on pre-silicon power data and validate against post-silicon measurements.
• Propose, enhance and maintain power analysis, optimization and modeling methodologies and flows.

Qualifications

• Must have extensive hands-on experience in power analysis, estimation, and optimization using industry standard tools such as PTPX and PowerArtist.
• Knowledge and experience with high performance and low power designs.
• Strong knowledge in the entire low power, high performance ASIC/SoC design flows (micro-architecture, RTL design, verification, synthesis, timing/STA, UPF, CLP, LEC formal verification, DFT, physical design.)
• Hands-on experience in writing scripts for automation and data analysis. (Shell, Perl, Tcl, Python, etc.)
• Knowledge and experience in data analysis and data science a plus but not required. (Pandas, Numpy, etc.)
• Bachelor's degree in Electrical Engineering, Computer Science, Computer Engineering, or related field

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