RTL Design - Peripheral(Sr Staff)
Job Description
- Ability to make schedule estimates
- People management experience
- Understanding of constraint development and timing closure
- Experience in Synthesis / Understanding of timing concepts
- Experience in System Verilog, Verilog, C/C++, Perl and Python
- Ability to lead a small design team
- Work independently on peripheral IPs
- Develop design and microarchitecture solutions
- Guide and mentor junior team members
- Engage with external teams to drive/resolve cross-team dependencies
- Take complete responsibility for one or more projects and drive independently
- 12+ years of work experience in ASIC IP cores design
- Knowledge of AMBA protocols (AXI, AHB, APB)
- Knowledge of SoC clocking/reset/debug architecture and peripherals (USB/PCIE/Ethernet)
- Hands-on experience in Low power design
- Hands-on experience in Multi Clock designs and Asynchronous interface
- Experience in using ASIC development tools such as Lint, CDC, Design compiler, and Primetime
- Strong experience in micro architecting RTL design from high-level design specification
- Excellent problem-solving skills
- Strong communication and teamwork skills
- Self-driven, needs to work with minimum supervision
- World-class health benefit options providing world-class coverage to employees and their eligible dependents
- Programs designed to help employees build and prepare for a financially secure future
- Self and family resources to build emotional/mental strength and resilience and define purpose
- Wellbeing programs and resources to help employees Live+Well and Work+Well
- Continuous learning and development programs
- Tuition reimbursement
- Mentorships
Job Posting Date
2025-09-26
Company:
Qualcomm India Private Limited
Job Area:
Engineering Group, Engineering Group > Hardware Engineering
General Summary:
Job Description
Responsibilities will include
- To be strong designer who is able to work independent on one of the peripheral IP’s
- come up with design and microarchitecture solutions
- guide/mentor juniors
- engage with external teams to drive/resolve cross team dependencies.
- Take complete responsibility of one or more project and drive that independently.
- Being able to make schedule estimates is a plus.
- People management experience is a plus
Skills & Requirements needed
- 12+ years of work experience in ASIC IP cores design
- Required: Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering
- Knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB/PCIE/Ethernet preferred.
- Work closely with the SoC verification and validation teams for pre/post Silicon debug
- Hands on experience in Low power design is required
- Hands on experience in Multi Clock designs, Asynchronous interface is a must.
- Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required.
- Understanding of constraint development and timing closure is a plus.
- Experience in Synthesis / Understanding of timing concepts is a plus.
- Strong experience in micro architecting RTL design from high level design specification.
- Excellent problem solving skills, strong communication and team work skills are mandatory.
- Self-driven, needs to work with minimum supervision.
- Experience in System Verilog, Verilog, C/C++, Perl and Python is a plus
- Ability to lead a small design team.
Minimum Qualifications:
• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
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