Senior Staff DDR/PCIE High Speed Interface IP Physical Design Engineer
Job Description
- Design level knowledge to optimize the implementation for PPPA
- 12 to 16 years of experience in physical design from product-based companies
- DDRPhy /PCIE-high speed interface PD or 3DIC Expertise
- Timing Signoff experience with SNPS/CDNS tools
- PDN: IR signoff and Physical verification knowledge
- Automation skills python/Perl/TCL
- RDL-design + Bump Spec understanding for smooth SoC PDN integration and signoff
- Proficiency in automation to drive improvements in PPA
- Experience working on multiple technology nodes in advanced processes
- Experience in low power design implementation, including Unified Power Format (UPF), multi-voltage domains, and power gating
- Familiarity with ASIC design flows and physical design methodologies
- World-class health benefit options providing world-class coverage to employees and their eligible dependents
- Programs designed to help employees build and prepare for a financially secure future
- Self and family resources to help build emotional/mental strength and resilience, as well as define purpose
- Wellbeing programs and resources to help employees Live+Well and Work+Well
- Continuous learning and development programs
- Tuition reimbursement
- Mentorships
Job Posting Date
2025-09-26
Job Area:
Engineering Group, Engineering Group > Hardware Engineering
General Summary:
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.
Minimum Qualifications:
• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
Job Description:
- 12 to 16 years of experience in physical design from product-based companies.
- DDRPhy /PCIE-high speed interface PD or 3DIC Expertise
- Timing Signoff experience with SNPS/CDNS tools
- PDN: IR signoff and Physical verification knowledge
- Automation skills python/Perl/TCL
- RDL-design + Bump Spec understanding for smooth SoC PDN integration and signoff
- Proficiency in automation to drive improvements in PPA
- Experience working on multiple technology nodes in advanced processes.
- Experience in low power design implementation, including Unified Power Format (UPF), multi-voltage domains, and power gating.
- Familiarity with ASIC design flows and physical design methodologies.
Good to Have:
- Design level knowledge to optimize the implementation for PPPA
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