PDK Enablement Engineering Specialist

17 Minutes ago • All levels • $89,600 PA - $166,400 PA

Software Development & Engineering

Job Description

As a PDK enablement engineering specialist, you will provide and support the tools and foundry files to enable the circuit implementation teams who build circuits used in cars, cell phones, data centers, etc. using the latest fabrication technologies: finfet, gate all-around, and using the latest Cadence software tools, including AI. Cadence Design Systems is seeking PDK enablement engineering specialists to enable foundry PDKs and support the growing analog design and custom layout team building IP using Cadence design tools to build high speed interfaces used in chips found in cars, cell phones, data centers, etc.

Good To Have:

Exposure to Cadence Virtuoso Layout and physical verification tools
Knowledge of Cadence Composer Schematic and Virtuoso Layout design tools and physical simulation and verification tools

Must Have:

BSEE or MSEE degree
Previous experience in PDK enablement
Knowledge of analog design and layout tools and flows
Excellent understanding of circuit design and layout

Perks:

Paid vacation and paid holidays
401(k) plan with employer match
Employee stock purchase plan
Variety of medical, dental and vision plan options
Incentive compensation: bonus, equity, and benefits

Add these skills to join the top 1% applicants for this job

communication

team-player

game-texts

quality-control

Job Description Summary

Job description

Cadence Design Systems is seeking PDK enablement engineering specialists to enable foundry PDKs and support the growing analog design and custom layout team building IP using the Cadence design tools (Virtuoso, Pegasus, Quantus, etc.) to build high speed interfaces used in chips found in cars, cell phones, data centers, etc.

You will get the opportunity to collaborate with circuit implementation experts to contribute to the development of exciting chips, work with the best-in-class EDA tools and interact with the Cadence engineering team using developing those tools to improve those tools.

The PDKs installed cover the latest technologies offered from all leading edge foundries in gate all-around and finfet nodes, as well as 2D and 2.5D packaging as well as 3D IC stacking.

PDK enablement task

The PDK enablement team is a part of the Cadence Design IP development group responsible for downloading, formatting, installing, QA and testing, releasing, and maintaining foundry data.

We analyze initial PDKs and following versions to understand the impact of the design PDK, models, DRC, LVS and extraction rules and decks, reliability requirements on design and share this knowledge with the design teams.

Examples of foundry data include physical verification decks, device models, extraction tech files, and Virtuoso PDKs. Those are the fundamental building blocks on which all the design teams rely to build their circuits.

We also create and use existing automation and regression routines to ease the installation and ensure the operation of collateral with various tool versions. The quality, accuracy and reliability of the PDK is critical to the efficiency and quality of the circuit design.

We customize the foundry collateral to improve the design team efficiency and the design quality.

The team interacts with the foundries about the PDK and foundry data, discussing novelties, issues, bugs, etc.

The team also interacts with Cadence R&D teams on tool development, based on PDK learnings.