Physical Design and Integration Engineer

Positions are open for full-time in the ares of physical design and integration from sub-system level to full chip level, involving all aspects of physical design partition and integration functions.

Responsibilities

• Own sub-system level or full chip level physical design integration, particularly focusing on design partition/integration, pin arrangement, feedthrough creation, clock/power grid planning.
• Be responsible for design integration and signoff coordination at sub-system or full chip level
• Evaluate/implementation physical design for channel, particularly for route ability and repeater planning
• Work with block or sub-system owners across the whole design cycles to drive design closure and design release/integration
• Participate flow/methodology development with CAD team

Requirements

• Experience in design partitioning, budgeting, pin planning with multiple takeout experience
• Knowledge using synthesis, place & route, analysis and verification CAD tools.
• Familiarity with logic & physical design principles to drive low-power & higher-performance designs.
• Knowledge of scripting in some of these languages: Unix, Perl, Python, and TCL
• Good understanding of device physics and experience in deep sub-micron technologies
• Knowledge of Verilog and SystemVerilog
• Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
• Ability to work well in a team and be productive under aggressive schedules.

Education and Experience

PhD, Master’s Degree or Bachelor’s Degree in technical subject area with more than five years of experience in relevant areas.