Senior Memory Design Engineer

1 Year ago • 8-10 Years • Software Development & Engineering

Job Summary

Job Description

Rivos Custom Circuits team is looking for motivated individuals to develop state-of-the-art custom SRAM memories, Register file memories, and compiled memories. The goal is to improve circuit performance, optimize dynamic and static power, and support silicon bring-up. This role is central to cutting-edge circuit design, requiring collaboration across disciplines to ensure quick product market entry. Responsibilities include designing and delivering custom circuits from scratch, transistor-level circuit design, simulation, equivalence checking, PPA trade-off analysis, low power design techniques, and characterization for timing, noise, and power. The ideal candidate will have extensive experience in custom circuit design from RTL to GDS for CPU and SoC applications, successfully designing high-performance SRAM memories, register files, compilers, data paths, and standard cells in advanced FinFET technologies. Experience with custom circuit tool flows, device physics, process technology, power gating, advanced process design rules, mask design supervision, automation development, and post-silicon test and debug is crucial. Strong problem-solving skills and excellent communication are essential for working effectively in a team under tight schedules.
Must have:
  • 12-15 years custom circuit design experience
  • Experience designing high performance SRAM memories
  • Experience in advanced FinFET technology nodes
  • Solid custom circuit tool flow experience
  • Understanding of device physics and process technology
  • Experience with advanced process design rules
  • Excellent problem solving skills
  • Excellent written and verbal communication
Good to have:
  • RTL-GDS for CPU and SoC applications
  • Register file memories design
  • SRAM compilers design
  • Data path designs
  • Standard cells design
  • Low power and power gating techniques
  • Mask design supervision
  • Automation development for compilers
  • Post-Silicon test and debug experience

Job Details

Rivos Custom Circuits team is seeking highly motivated candidates to develop state of the art custom SRAM memories, Register file memories, and compiled memories  to improve circuit performance, optimize dynamic and static power and support silicon bring up. The role will be at the center of a state-of-the art circuit design effort, interfacing with all disciplines and have a critical impact on getting products to market quickly.  The qualified candidate will be responsible for designing and delivering custom circuits from scratch.  Candidates must have 8-10 years of experience in transistor level circuit design, circuit simulation, equivalence checking,  PPA trade off analysis, low power design techniques, timing, noise and power characterization.

Key Qualifications

    • The ideal candidate will have 12-15 years of custom circuit design experience from RTL-GDS for CPU and SoC applications
    • Prior experience and proven success of successfully designing high performance SRAM memories, Register file memories, SRAM compilers, data path designs and standard cells
    • Experience designing transistor-level custom circuits in advanced FinFET technology nodes
    • Must have a solid experience with the custom circuit tool flows for delivering design collaterals
    • A solid understanding of device physics, process technology and circuit design techniques for high performance, low power, and power gating
    • Experience with advanced process design rules and supervising mask design
    • Knowledge developing automation for compilers and standard cells
    • Post-Silicon test and debug experience
    • Ability to work well in a team and be productive under aggressive schedules.
    • Excellent problem solving, written and verbal communication

Responsibilities

    • Drive design and development of SRAM, register file, custom cells to enable high performance and low power designs
    • Work with microarchitecture team to gather specifications and drive optimal implementation 
    • Conduct early sizing estimates and PPA analysis . 
    • Design entry and simulations for optimal design sizing.
    • Design equivalence checking using the latest industry standard LEC tools
    • Work closely with mask designers on custom design implementation, DFM and  yield enhancement features
    • Deliver high quality design collateral 
    • Collaborate with the CPU and SoC Physical design teams on floorplanning, placement, timing and power closure of the custom design
    • Interact with technology team, participate in developing design and test plans Collaborate with CAD teams and drive design flow enhancements

Education and Experience

    • Master’s Degree or Bachelor’s Degree with  12-15 years of experience

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About The Company

Santa Clara, California, United States (Hybrid)

Santa Clara, California, United States (Hybrid)

Hsinchu, Hsinchu City, Taiwan (Hybrid)

Santa Clara, California, United States (On-Site)

Santa Clara, California, United States (Hybrid)

Santa Clara, California, United States (Hybrid)

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