The job involves full-time CPU physical design roles, covering unit to chip levels and all physical design functions including place & route, timing, floorplan, clocking, and power. Responsibilities include owning block-level design from RTL-to-GDSII, driving synthesis, floor-planning, place & route, timing closure, and signoff. It also entails working with micro-architects for feasibility studies and PPA tradeoffs, developing physical design methodologies, and collaborating with multi-functional teams for validation and signoff flows like Timing, Power, EM/IR, and PDV.