Silicon Power Engineer

1 Month ago • 4-7 Years

System Design

Job Description

The Rivos Power team is seeking a highly motivated engineer to develop and strategically drive state-of-the-art power modeling and optimization across our CPU and SoC blocks. This role involves working in an innovative, collaborative, and high-growth environment, focusing on the full spectrum of silicon power reduction, including power analysis, performance benchmarking, and design optimization from microarchitecture to physical implementation.

Good To Have:

Familiarity with the RISC-V architecture

Must Have:

Model and analyze power consumption for various workloads on custom silicon.
Define overall power requirements with CPU Architecture, Performance, and Implementation teams.
Analyze power and performance trade-offs and recommend power reduction strategies.
Create targeted test vectors for accurate simulation.
Own end-to-end power simulation process (analysis, tuning, correlation, presentation).
Partner with CAD and Physical Design teams to enhance power estimation methodologies.
Bachelor's or Master's degree in EE/EECS.
4-7 years of direct experience in power-aware design (analysis, benchmarking, modeling, simulation).
Strong working knowledge of CPU architectures and workload modeling for power analysis.
Proficiency with Verilog and SystemVerilog RTL coding.
Experience with complete silicon design flow and PPA trade-offs.
Hands-on experience with state-of-the-art EDA tools for power modeling and simulation.
Strong scripting skills in Python, TCL.
Ability to solve problems dynamically, innovate, drive decisions, and lead team efforts.

Add these skills to join the top 1% applicants for this job

cad-computer-aided-design

game-texts

python

The Rivos Power team is seeking a highly motivated engineer to develop and strategically drive state-of-the-art power modeling and optimization across our CPU and SoC blocks. In this role, you will have the opportunity to work in an innovative, collaborative, and high-growth environment. The ideal candidate will possess in-depth experience in the full spectrum of silicon power reduction. This includes a foundation in solid power analysis, performance benchmarking, and design optimization at all levels—from microarchitecture and physical implementation to standard power-performance benchmarking.

What You'll Do:

Model and analyze power consumption for various workloads on custom silicon, working closely with the CPU Architecture, Performance, and Implementation teams to define overall power requirements.
Analyze power and performance trade-offs, drive detailed cost-benefit analyses, and make recommendations for power reduction strategies.
Collaborate with the Performance, Design Verification, and RTL teams to create targeted test vectors that model appropriate workloads and functionality scenarios for accurate simulation.
Own the end-to-end power simulation process, including analysis, tuning, correlation, and presenting results to the Architecture, Logic Design, and Physical Design teams.
Partner with the CAD and Physical Design teams to enhance power estimation methodologies, simulation flows, and regression analysis.

What You'll Bring:

A Bachelor's or Master's degree in EE/EECS with 4-7 years of relevant industry experience.
4 to 7 years of direct experience in power-aware design, including analysis, benchmarking, modeling, and simulation.
Strong working knowledge of CPU architectures and workload modeling for power analysis. Familiarity with the RISC-V architecture is a significant plus.
Proficiency with Verilog and SystemVerilog RTL coding.
Experience with the complete silicon design flow and evaluating power, performance, and area (PPA) trade-offs at the architectural, logic, and circuit levels.
Hands-on experience with state-of-the-art EDA tools for gate-level and transistor-level power modeling and simulation.
Strong scripting skills in Python, TCL, or other relevant languages.
A proven ability to solve problems dynamically, innovate, drive decisions, and lead team efforts to deliver results under aggressive schedules.