Silicon Verification - Intern

1 Month ago • All levels
Quality Assurance

Job Description

Rivos is seeking a Silicon Verification Intern for a 6-month (or more) co-op/internship in Bangalore, India. This role involves verifying CPU and SOC designs from unit to chip level, covering functional, microarchitecture, performance, and formal verification. The intern will work with architecture and RTL designers, develop test plans, environments, and tests, and debug failures to ensure design correctness.
Good To Have:
  • Basic knowledge of formal verification methodology
  • Excellent knowledge of one of the scripting languages such as Python, TCL
Must Have:
  • Work closely with architecture and RTL designers on verifying the functionality correctness of the design
  • Reviewing Architecture and Design Specifications
  • Develop test plans and test environments
  • Develop tests in assembly, C/C++, or vectors
  • Develop coverage monitors and analyze coverage
  • Develop checkers in SystemVerilog or C-base transactors
  • Write assertions and apply formal verification to the design
  • Implementing test benches, generating directed/constrained random tests
  • Debugging failures, running simulations, tracking bugs
  • Handling schedules and supporting multi-functional engineering effort
  • Assisting in verification flows, automation scripts and regressions

Add these skills to join the top 1% applicants for this job

problem-solving
cpp
game-texts
test-coverage
python

Positions are open for immediate Co-op/internship(6 months or more duration) in the areas of CPU and SOC verification from unit level to chip level as well as all aspects of verification such as functional, microarchitecture, performance, and formal.

We are looking for all levels of talent, from entrance to advanced level of experience.

Responsibilities

  • Work closely with architecture and RTL designers on verifying the functionality correctness of the design
  • Reviewing Architecture and Design Specifications
  • Develop test plans and test environments
  • Develop tests in assembly, C/C++, or vectors according to test plans
  • Develop coverage monitors and analyze coverage to ensure all the test cases in the plans are covered
  • Develop checkers in SystemVerilog or C-base transactors to verify the design
  • Write assertions and apply formal verification to the designImplementing test benches, generating directed/constrained random tests
  • Debugging failures, running simulations, tracking bugs
  • Handling schedules and supporting multi-functional engineering effortAssisting in verification flows, automation scripts and regressions

Requirements

  • In-depth knowledge of digital logic design, CPU/SOC architecture and microarchitecture.
  • Sophisticated knowledge of SystemVerilog.
  • Experienced level knowledge C/C++.Relevant knowledge of verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection.
  • Basic knowledge of formal verification methodology is a plus.
  • Excellent knowledge of one of the scripting languages such as Python, TCL is a plus.
  • Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
  • Ability to work well in a team and be productive under aggressive schedules.

Education and Experience

  • PhD, Master’s Degree or Bachelor’s Degree in technical subject area.

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