As a Sr. SLT (System Level Test) engineer, this role will be responsible for building SLT program to enable HVM shipment of our Silicon. Key responsibilities include developing SLT test programs, designing test hardware, integrating system components, characterizing device performance, debugging failures, and optimizing test time. The role also involves collaborating with engineering teams for coverage improvement, supporting yield analysis, and providing manufacturing support for SLT solutions.
Must Have:- Develop SLT test programs, scripts, and automation.
- Design and implement test hardware and fixture solutions.
- Characterize device performance at system level.
- Debug test failures and determine root cause.
- Optimize test time and throughput for HVM.
- Support yield analysis and defect screening strategies.
- Transfer SLT solutions from engineering to production.
- 8-10 years in semiconductor SLT, validation, or ATE test engineering.
- Strong knowledge of system-level hardware architecture.
- Proficiency in scripting languages (Python, Perl).
- Hands-on experience with SLT platforms.