Power UPF Methodology Engineer

As a Power UPF Methodology Engineer in the Digital Design Engineering group, you will be responsible for developing innovative solutions and bringing forward-thinking ideas to reality. You will work on designing state-of-the-art ASICs, driving transistor-level power ERC sign-off and UPF implementation & verification for mobile SOCs. Your role will involve collaborating with various teams, integrating new insights, and supporting transistor-level power ERC sign-off for digital and mixed-signal designs. You will also drive UPF implementation and verification for mobile SOCs, enhance the current power sign-off flow, and expand power sign-off methodology for next-generation mobile products. Key responsibilities include driving mixed-signal IP power ERC and power intent verification, ensuring coverage of power intent across static and dynamic checking methodologies, defining and developing power ERC frameworks, bringing up power intent checking flows, driving power intent & power ERC sign-off for tape-out, and liaising with CAD and physical design verification teams.