Power UPF Methodology Engineer

Apple

| Beaverton, Oregon, United States (On Site) | Full Time | 5 months ago

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Job Summary

As a Power UPF Methodology Engineer in the Digital Design Engineering group, you will be responsible for developing innovative solutions and bringing forward-thinking ideas to reality. You will work on designing state-of-the-art ASICs, driving transistor-level power ERC sign-off and UPF implementation & verification for mobile SOCs. Your role will involve collaborating with various teams, integrating new insights, and supporting transistor-level power ERC sign-off for digital and mixed-signal designs. You will also drive UPF implementation and verification for mobile SOCs, enhance the current power sign-off flow, and expand power sign-off methodology for next-generation mobile products. Key responsibilities include driving mixed-signal IP power ERC and power intent verification, ensuring coverage of power intent across static and dynamic checking methodologies, defining and developing power ERC frameworks, bringing up power intent checking flows, driving power intent & power ERC sign-off for tape-out, and liaising with CAD and physical design verification teams.

Must Have

Drive transistor level power ERC sign-off
Drive UPF implementation & verification
Develop transistor level power ERC sign-off
Drive UPF implementation and verification
Support transistor level power ERC sign-off
Drive power ERC sign-off at full-chip level
Expand power sign-off methodology
Drive Mixed signal IP power ERC
Drive power intent verification
Drive coverage of power intent
Define and develop power ERC framework
Bring up power intent checking flows
Drive power intent sign-off
Drive power ERC sign-off for tape-out
Liaise with CAD and physical design verification team

Job Description

Do you have a passion for crafting entirely new solutions? As part of our Digital Design Engineering group, you’ll take imaginative and revolutionary ideas and determine how to turn them into reality! You and your team will apply engineering fundamentals and groundbreaking efforts, bringing forward-thinking ideas to the real world. Join us, and you’ll help design the tools that allow us to bring customers experiences they’ve never before envisioned! You will be part of an exciting silicon design group that is responsible for designing state-of-the-art ASICs. We have an extraordinary opportunity for Power UPF Engineers, who will drive transistor level power ERC sign-off and power intent-UPF implementation & verification on mobile SOCs.

Imagine yourself at the center of our SOC design effort, collaborating with all fields, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new insights, as well as work with a team of hardworking engineers. The main responsibility of this role is to develop and support transistor level power ERC sign-off for digital and mixed signal designs, drive power ERC sign-off at full-chip level, drive UPF implementation and verification for mobile SOCs and make current power sign-off flow more robust and expand power sign-off methodology for next generation mobile products, including:

- Drive Mixed signal IP power ERC and power intent verification.

- Drive coverage of power intent across static and dynamic checking methodologies.

- Define and develop power ERC framework for new projects.

- Bring up power intent checking flows on new projects.

- Drive power intent & power ERC sign-off for tape-out.

- Liaison with CAD and physical design verification team for debugging any power ERC and power intent flow issues.