RTL Design Engineer (ASIC, IP Design)

3 Minutes ago • 4-20 Years
Software Development & Engineering

Job Description

Marvell's Switch Business Unit designs next-generation datacenter and enterprise System-On-Chip switch processors. This role involves completely owning egress processor IP design, working with architecture teams for feature enhancements, implementing specifications using RTL coding, ensuring quality criteria, and collaborating with physical design and verification teams. The role requires familiarity with Digital IC design methodologies, ASIC design flows, and state-of-the-art design tools.
Good To Have:
  • Networking knowledge.
  • Knowledge of scripting languages like PERL, Python.
  • Experience with Ethernet protocols (IEEE 802.3, 802.1Q, 802.1D, Routing protocols).
  • L2 / L3 / L4 Ethernet protocol knowledge.
  • Experience with Encryption / Authentication algorithms.
  • Knowledge of Precision Time Protocol (PTP, IEEE-1588).
  • Knowledge of GIT version control system.
  • Good learning, problem-solving, interpersonal, and communication skills.
  • Ability to be a part of a team, working in cooperation.
  • Self-motivated team player able to thrive in a fast-paced engineering environment.
Must Have:
  • Own egress processor IP design.
  • Work with architecture team for feature enhancements.
  • Implement specifications using RTL coding techniques.
  • Ensure all quality criteria are met.
  • Familiarity with Digital IC design methodologies and ASIC design flows.
  • Experience with state-of-the-art design tools.
  • Collaborate with physical design teams for synthesis and timing signoff.
  • Work with Verification team on pre-silicon verification tasks.
  • Strong knowledge of HDL and Verilog coding.
  • Strong knowledge of logic synthesis and timing analysis.
  • Master’s/PhD/Bachelor’s degree in CS/EE or related fields.
  • 4 to 20 years of relevant industry experience.
  • Experience with digital design microarchitecture development.
  • Design/RTL experience in Verilog or SV.
  • Experience with logic synthesis, constraint development, backend flow, and static timing analysis.
Perks:
  • Competitive compensation
  • Great benefits
  • Workstyle within an environment of shared collaboration, transparency, and inclusivity
  • Tools and resources needed to succeed
  • Opportunities to grow and develop

Add these skills to join the top 1% applicants for this job

communication
team-player
github
game-texts
test-coverage
networking
git
python
algorithms
perl

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

The Switch Business Unit in Marvell designs and develops the next generation datacenter and enterprise System-On-Chip switch processors on leading edge process technology. We develop the architecture, collaborate on IP development, create the physical design, develop switching solutions and work with the world’s leading data center and enterprise companies to bring next generation networking to reality.

What You Can Expect

You will completely own the egress processor IP design Including:

  • Closely working with architecture team to understand the feature enhancement needs.
  • Implement a specification using RTL coding techniques.
  • Ensuring all quality criteria are met.
  • Must be familiar with Digital IC design methodologies, understand all stages of ASIC design flows, and experienced with state-of-the-art design tools.
  • Work with the physical design teams for synthesis and timing signoff.
  • Work with the Verification team on pre-silicon verification tasks such as reviewing the verification test plan, coverage analysis, and full-chip simulation and related debug.
  • Strong Knowledge of HDL and experience in Verilog coding, Perform RTL coding,
  • Strong Knowledge of logic synthesis and timing analysis.
  • Networking knowledge is a plus.

What We're Looking For

  • Master’s degree and/or PhD/Bachelor’s degree in Computer Science, Electrical Engineering or related fields with 4 to 20 years’ of relevant industry experience.
  • Experience with digital design microarchitecture development is a must.
  • Design/RTL experience in Verilog or SV is a must.
  • Experience with logic synthesis, synthesis constraint development and backend flow and static timing analysis.
  • Knowledge of scripting languages, such as PERL, Python
  • Ethernet protocols (IEEE 802.3, 802.1Q, 802.1D, Routing protocols) preferred.
  • L2 / L3 / L4 Ethernet protocol knowledge
  • Encryption / Authentication algorithms.
  • Precision Time Protocol (PTP, IEEE-1588)
  • Knowledge of GIT version control system
  • Good learning , problem solving interpersonal and communication skills.
  • * Ability to be a part of a team, working in cooperation.
  • Self-motivated team player able to thrive in a fast-paced engineering environment.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity

As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.

Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.

Export Control Notice

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

#LI-RV1

Set alerts for more jobs like RTL Design Engineer (ASIC, IP Design)
Set alerts for new jobs by Marvell
Set alerts for new Software Development & Engineering jobs in India
Set alerts for new jobs in India
Set alerts for Software Development & Engineering (Remote) jobs
Contact Us
hello@outscal.com
Made in INDIA 💛💙