Signal and Power Integrity Engineer

Responsibilities:

• Engage with customers and product managers to understand product requirements; research and analyze potential memory technologies; engage directly with memory vendors and suppliers to evaluate options and drive requirements; quantify the tradeoffs
• Recommend technical direction with robust justification.
• Effectively communicate and collaboratively engage with the other SoC & IP architects, designers, systems engineers, product managers, and software teams to define Memory System solutions enabling market-leading Data Center products.
• Perform various IO analyses using established methodologies, potentially from model extraction through simulation and reporting of conclusions. IO types include a variety of serial and memory interfaces.
• Apply established methodologies to analyze IO power distribution in product development and reference systems.
• Perform package extraction for time domain and frequency domain SIPI analysis and provide design guidelines for the package design.
• Create clear and complete documentation of results.

Minimum Qualifications:

• 8+ years of experience with 5+ years in DDR/SerDes in Package/PCB/System Design related to compute/server standards.
• Experience in electromagnetics and a solid background in transmission line theory and crosstalk.
• Proficiency in field solvers such as HFSS, Q3D, Sentinel-PSI, and Clarity, and SPICE transient simulation (ADS, Hspice), including use of IBIS and IBIS AMI models.
• Outstanding memory architecture expertise on SRAM, DRAM, DDR, LPDDR, HBM, GDDR and emerging memory technologies such as STT-MRAM, PIM, etc.
• Understanding internal memory technology organization, including DRAM bank & array arrangement, rows and columns, row buffer operation, internal data bus pathways, refresh, power state control, etc.
• Understanding of memory controller architecture, memory scheduling, prioritization and QoS
• Understanding memory PHY parameters and tradeoffs, including for LPDDR, DDR, and HBM
• Fluid knowledge of one or more JEDEC standards such as LPDDR, DDR, or HBM, and the ability to analyze such standards and drive recommendations
• Experience working with or working at the major DRAM and other memory vendors
• Background in memory systems and computer architecture to understand the tradeoffs among memory bandwidth, latency, performance, power, SoC area
• Understanding memory technology parameters such as reliability, thermals, ECC, encryption, etc.
• PHY shoreline, packaging, stacking, etc.
• Excellent communication, documentation, and interpersonal skills with ability to convey proposals and interact effectively across a distributed multi-discipline organization
• Ability to abstract appropriately to define problems and solution, and make data-drive decisions
• Record of quantitative analysis using (and developing) tools such as high-level calculators & spreadsheets, DRAM timing simulators, profilers, functional and performance simulators, etc.
• Experience driving JEDEC or similar standardization is a plus

Preferred Qualifications:

• Experience in DDR design specifications such as DDR and LPDDR
• Experience in SerDes design specifications such as PCIe, USB, UFS, and MIPI.
• Experience in Matlab to automate existing simulation flow.
• Experience in programming languages (C/C++) or scripting languages (Perl/Python) is a plus.
• Master’s or Ph.D. degree with 8+ years of industry experience.

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