SOC Design Engineer- Sr Eng

Job Description

• 8 to 11 years of work experience in ASIC/SoC Design
• Experience in Logic design /micro-architecture / RTL coding is a must.
• Must have hands on experience with SoC design and integration for complex SoCs.
• Experience in Verilog/System-Verilog is a must.
• knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC.
• Understanding of Memory controller designs and microprocessors is an added advantage
• Work closely with the SoC verification and validation teams for pre/post Silicon debug
• Hands on experience in Low power SoC design is required
• Hands on experience in Multi Clock designs, Asynchronous interface is a must.
• Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required.
• Understanding of constraint development and timing closure is a plus.
• Experience in Synthesis / Understanding of timing concepts is a plus.
• Experience creating padring and working with the chip level floorplan team is an added advantage.
• Excellent oral and written communications skills
• Proactive, creative, curious, motivated to learn and contribute with good collaboration skills.

Required: Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering.