SoC Physical Design Verification Engineer

In this highly visible role, you will be part of a critical team responsible for physical verification of an SOC.

As a member of our physical design team, you will perform various types of physical verification checks such as LVS, DRC, design-for-manufacturing, design-for-yield, and other lithography and electrical checks at the chip and block level. Responsibilities expected will include:

• Driving full-chip physical verification flow methodology for Apple SoCs, starting from initial floorplanning phase through final tapeout.
• Setup and validation of PDV flows for block and full chip levels, including optimizations in partnership with cross functional groups such as Technology and CAD teams.
• Close collaboration with PNR, custom design, and IP teams to identify PDV issues starting from early milestones and drive solutions that optimize for PPA and efficient design closure.
• Driving full chip implementation and verification methodologies for ESD protection strategies including digital, analog and mixed signal back-end design verification.
• Serve as a technical expert and mentor within the organization, providing guidance on complex verification challenges and fostering the growth of early career engineers.
• Proactively identify and address execution risks, communicate status clearly to leadership, and drive issues to resolution with a high degree of autonomy.
• Cross functional collaboration with package, floorplan, and other analysis teams for padring, bump and RDL designs.

• Minimum BS and 10+ years of relevant industry experience.
• Proficient with industry-standard EDA tools such as Mentor Calibre, and/or Synopsys ICV.
• Experience with scripting skills in Python, Tcl, and/or Perl, calibre-SVRF through deployed automation or verification flows.

• Proven track record of taping out multiple complex SoCs in advanced tech-nodes.
• Understanding of the device physics and how it applies to back-end verification challenges associated with advanced nodes, including complex design rules.
• Experience in debugging and resolving highly complex LVS and DRC issues at the full-chip and block level.
• Demonstrated ability to lead technical initiatives, mentor early career engineers, and drive methodologies from concept to production.
• Experience with ESD protection strategies and digital, analog, and mixed signal design integration verification.
• Experience with padring placement, Bump, RDL, and package design methodologies and verification checks.
• Experience with industry-standard electrical analysis tools such as PERC, RedHawk, PathFinder, Totem, and/or Voltus used in ESD signoff checks.
• Layout design experience.