SoC RTL Security Design Engineer
Job Summary
Job Description
- 3+ years RTL coding (Verilog/SystemVerilog)
- Experience with EDA tools
- Security design experience
- SystemVerilog RTL development
- Collaboration with cross-functional teams
- Master's/PhD in relevant field
- Experience with security IPs
- Scripting languages (Tcl, Python, Perl)
- Understanding of digital design fundamentals
- Bonus
- Equity
- Benefits
5 skills required
Job Details
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 3 years of experience with RTL coding using Verilog/SystemVerilog.
- Experience with industry-standard EDA tools for simulation, synthesis and power analysis.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- 5 years of experience in ASIC design with 3 years of experience working on security design.
- Experience interacting with software, system hardware, and other cross-functional teams.
- Experience developing and integrating security IPs into an SoC.
- Experience with scripting languages (e.g., Tcl, Python or Perl).
- Understanding of digital design fundamentals, including synchronous and asynchronous logic, state machines and bus protocols.
About the job
The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
- Create and review the security subsystem's design microarchitecture specifications.
- Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
- Work with architecture and power teams to evaluate security features and their impact.
- Work with design validation (DV) teams to create test plans to verify, and debug design RTL.
- Work with physical design teams to ensure design meets physical requirements and timing closure.
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About The Company
A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.
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