Sr Application Engineer

The Sr Application Engineer will be responsible for physical design implementation tasks including floor planning, power grid design, place and route, clock tree synthesis, timing closure, and physical verification. This role involves working on challenging low power and high-speed designs at the latest technology nodes, participating in methodology development, and collaborating with the RTL design team to ensure successful tapeouts. Candidates need 3+ years of experience in physical design and verification with solid knowledge of ASIC design flow, low power design, DFT, timing analysis, and various signoff procedures.

Must Have

• Perform physical design implementation (floor planning, power grid, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification, EM/IR signoff, DFM Closure).
• Work on low power and high-speed designs at latest technology nodes.
• Participate in or lead next generation physical design, methodology and flow development.
• Work closely with RTL design team for successful tapeouts.
• BS/MS in EE/CS with 3+ years of hands-on experience in physical design and verification.
• Experienced with ASIC design flow, hierarchical physical design strategies, and deep sub-micron technology issues.
• Solid knowledge on Low Power Design, DFT, static timing analysis and closure, data skew balancing, duty cycle adjustment, EM/IR-Drop/crosstalk analysis, formal verification, physical verification, DFM and P&R.
• Able to assume responsibility for a variety of technical tasks and to work independently.
• Able to be hands-on at all levels of design, with the ability to verify, test, and characterize own designs.
• Self-motivated, able to work as a team player, and good English communication skills.

• The candidate will perform the physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.
• The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed designs at the latest technology nodes.
• The responsibility of the candidate includes participating in or leading next generation physical design, methodology and flow development.
• The candidate will work closely with RTL design team to ensure successful tapeouts.

Requirement:

• BS/MS in EE/CS with 3+ years of hands-on experience in physical design and verification.
• Experienced with ASIC design flow, hierarchical physical design strategies, methodologies, and understand deep sub-micron technology issues.
• Solid knowledge on Low Power Design, DFT, static timing analysis and closure, data skew balancing, duty cycle adjustment, EM/IR-Drop/crosstalk analysis, formal verification, physical verification, DFM and P&R.
• Able to assume responsibility for a variety of technical tasks and to work independently
• Able to be hands-on at all levels of design, with the ability to verify, test, and characterize own designs
• Self-motivated, able to work as a team player, and good English communication skills